r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 327

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r5f21368sdfp

Manufacturer Part Number
r5f21368sdfp
Description
Renesas Mcu R8c Family / R8c/3xt-a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
17.3.2
Table 17.11
TOB Bit in TRCCR1 Register
In PWM mode, when the TRCGRA register is set as the period register and registers TRCGRB, TRCGRC, and
TRCGRD are set as duty registers, a PWM waveform is output from pins TRCIOB, TRCIOC, and TRCIOD
individually. A PWM waveform with up to three phases can be output. In this mode, the general register
functions as an output compare register. The initial output level of the corresponding pin is set according to the
values in bits TOA to TOD in the TRCCR1 register and bits POLB to POLD in the TRCCR2 register.
Table 17.11 lists the Initial Output Levels of TRCIOB Pin.
The output level is determined by bits POLB to POLD. When the POLB bit is 0 (output level is active low), the
TRCIOB output pin is set to low at compare match B and high at compare match A. When the POLB bit is 1
(output level is active high), the TRCIOB output pin is set to high at compare match B and low at compare
match A.
The setting values of PWM mode take precedence over those of registers TRCIOR0 and TRCIOR1. When the
values set in the period and duty registers are the same, the output value remains unchanged even if a compare
match occurs.
Figure 17.9 shows an Operation Example in PWM Mode.
PWM Mode
Preliminary document
Specifications in this document are tentative and subject to change.
Initial Output Levels of TRCIOB Pin
0
1
POLB Bit in TRCCR2 Register
0
1
0
1
Initial Output Level
1
0
0
1
Page 296 of 725
17. Timer RC

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