MC9S12E256VPVE Freescale Semiconductor, MC9S12E256VPVE Datasheet - Page 107

• Manufacturer Part Number: MC9S12E256VPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256VPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.4.1.3.2
The data compress command is used to check Flash code integrity by compressing data from a selected
portion of the Flash block into a signature analyzer. The starting address for the data compress operation
is defined by the address written during the command write sequence. The number of consecutive word
addresses compressed is defined by the data written during the command write sequence. If the data value
written is 0x0000, 64K addresses or 128 Kbytes will be compressed. After launching the data compress
command, the CCIF flag in the FSTAT register will set after the data compress operation has completed.
The number of bus cycles required to execute the data compress operation is equal to two times the number
of addresses read plus 20 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF
flag is set. After the CCIF flag is set, the signature generated by the data compress operation is available
in the FDATA register. The signature in the FDATA register can be compared to the expected signature
to determine the integrity of the selected data stored in the Flash block. If the last address of the Flash block
is reached during the data compress operation, data compression will continue with the starting address of
the Flash block.
In order to take corrective action, it is recommended that the data compress command be executed on a
Flash sector or subset of a Flash sector. If the data compress operation on a Flash sector returns an invalid
signature, the Flash sector must be erased using the sector erase command and then reprogrammed using
the program command.
The data compress command can be used to verify that a sector or sequential set of sectors are erased.
Freescale Semiconductor
Data Compress Command
Since the FDATA register (or data buffer) is written to as part of the data
compress operation, a command write sequence is not allowed to be
buffered behind a data compress command write sequence. The CBEIF flag
will not set after launching the data compress command to indicate that a
command must not be buffered behind it. If an attempt is made to start a new
command write sequence with a data compress operation active, the
ACCERR flag in the FSTAT register will be set. A new command write
sequence must only be started after reading the signature stored in the
FDATA register.
MC9S12E256 Data Sheet, Rev. 1.08
NOTE
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
107