MC9S12E256VPVE Freescale Semiconductor, MC9S12E256VPVE Datasheet - Page 162

IC MCU 256K FLASH 25MHZ 112-LQFP

MC9S12E256VPVE

Manufacturer Part Number
MC9S12E256VPVE
Description
IC MCU 256K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12E256VPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12E256VPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 3 Port Integration Module (PIM9E256V1)
3.6
3.6.1
Port AD generates an edge sensitive interrupt if enabled. It offers sixteen I/O pins with edge triggered
interrupt capability in wired-OR fashion. The interrupt enable as well as the sensitivity to rising or falling
edges can be individually configured on per pin basis. All eight bits/pins share the same interrupt vector.
Interrupts can be used with the pins configured as inputs (with the corresponding ATDDIEN1 bit set to 1)
or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. This external interrupt feature is capable to wake up the CPU when it is in stop or
wait mode.
A digital filter on each pin prevents pulses
interrupt. The minimum time varies over process conditions, temperature and voltage
Table
162
3-38).
Interrupts
General
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
1
These values include the spread of the oscillator frequency over temperature,
voltage and process.
Uncertain
Ignored
Pulse
Valid
Figure 3-51. Interrupt Glitch Filter on Port AD (PPS = 0)
t
Table 3-38. Pulse Detection Criteria
ifmin
3 < t
t
t
MC9S12E256 Data Sheet, Rev. 1.08
pulse
pulse
pulse
t
ifmax
<= 3
>= 4
(Figure
< 4
STOP
3-52) shorter than a specified time from generating an
Bus Clock
Bus Clock
Bus Clock
Unit
Mode
3.2 < t
t
pulse
t
pulse
pulse
<= 3.2
>= 10
STOP
< 10
1
Unit
Freescale Semiconductor
s
s
s
(Figure 3-51
and

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