MC9S12E256VPVE Freescale Semiconductor, MC9S12E256VPVE Datasheet - Page 349

• Manufacturer Part Number: MC9S12E256VPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256VPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.3.2.31 PMF Frequency Control C Register (PMFFQCC)
Read anytime and write only if MTG is set.
Freescale Semiconductor
Module Base + 0x0031
PWMRIEC
LDOKC
LDFQC
HALFC
Reset
Field
Field
7–4
1
0
3
W
R
Load Okay C — If MTG is clear, this bit reads zero and can not be written.
If MTG is set, this bit loads the PRSCC bits, the PMFMODC register and the PWMVAL4–5 registers into a set of
buffers. The buffered prescaler divisor C, PWM counter modulus C value, PWM4–5 pulse widths take effect at
the next PWM reload.
Set LDOKC by reading it when it is logic zero and then writing a logic one to it. LDOKC is automatically cleared
after the new values are loaded, or can be manually cleared before a reload by writing a logic zero to it. Reset
clears LDOKC.
0 Do not load new modulus C, prescaler C, and PWM4–5 values.
1 Load prescaler C, modulus C, and PWM4–5 values.
Note: Do not set PWMENC bit before setting the LDOKC bit and do not clear the LDOKC bit at the same time
PWM Reload Interrupt Enable C — If MTG is clear, this bit reads zero and cannot be written.
If MTG is set, this bit enables the PWMRFC flag to generate CPU interrupt requests.
0 PWMRFC CPU interrupt requests disabled
1 PWMRFC CPU interrupt requests enabled
Load Frequency C — This field selects the PWM load frequency according to
Section 11.4.7.2, “Load Frequency”
Note: The LDFQC field takes effect when the current load cycle is complete, regardless of the state of the load
Half Cycle Reload C — This bit enables half-cycle reloads in center-aligned PWM mode. This bit has no effect
on edge-aligned PWMs.
0 Half-cycle reloads disabled
1 Half-cycle reloads enabled
0
7
as setting the PWMENC bit.
okay bit, LDOKC. Reading the LDFQC field reads the buffered value and not necessarily the value
currently in effect.
Figure 11-37. PMF Frequency Control C Register (PMFFQCC)
Table 11-39. PMFENCC Field Descriptions (continued)
0
6
LDFQC
Table 11-40. PMFFQCC Field Descriptions
MC9S12E256 Data Sheet, Rev. 1.08
0
5
for more details.
Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
0
4
Description
Description
HALFC
3
0
0
2
PRSCC
Table
11-41. See
0
1
PWMRFC
0
0
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