MC9S12E256VPVE Freescale Semiconductor, MC9S12E256VPVE Datasheet - Page 481

• Manufacturer Part Number: MC9S12E256VPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256VPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.3.2.5
1
2
3
Freescale Semiconductor
EXTCMP
See
Current HCS12 implementations have PPAGE limited to 6 bits. Therefore, EXTCMP[5:4] should be set to 00.
Data page (DPAGE) and Extra page (EPAGE) are reserved for implementation on devices that support paged data and extra
space.
PAGSEL
PAGSEL
Reset
Field
10
11
7:6
5:0
00
01
Figure
W
R
3
2
16-10.
Page Selector Field — In both BKP and DBG mode, PAGSEL selects the type of paging as shown in
Table
DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and
11 will be interpreted as values of 00 and 01, respectively).
Comparator C Extended Compare Bits — The EXTCMP bits are used as comparison address bits as shown
in
Note: Comparator C can be used when the DBG module is configured for BKP mode. Extended addressing
Debug Comparator C Extended Register (DBGCCX)
0
7
Table 16-11
PAGSEL
16-11.
comparisons for comparator C use PAGSEL and will operate differently to the way that comparator A and
B operate in BKP mode.
(256 — 16K pages)
DPAGE (reserved)
(256 — 4K pages)
EPAGE (reserved)
(256 — 1K pages)
Normal (64k)
Figure 16-9. Debug Comparator C Extended Register (DBGCCX)
Description
PPAGE
along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core.
0
6
Table 16-10. DBGCCX Field Descriptions
Table 16-11. PAGSEL Decoding
MC9S12E256 Data Sheet, Rev. 1.08
0
5
EXTCMP[5:0] is compared to
EXTCMP[3:0] is compared to
EXTCMP[1:0] is compared to
address bits [21:16]
address bits [19:16]
address bits [17:16]
0
4
EXTCMP
Not used
Description
2
3
0
EXTCMP
1
DPAGE / XAB[21:14] becomes address
EPAGE / XAB[21:14] becomes address
PPAGE[7:0] / XAB[21:14] becomes
0
2
Chapter 16 Debug Module (DBGV1)
address bits [21:14]
No paged memory
bits [19:12]
bits [17:10]
Comment
0
1
1
0
0
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