MC9S12E256VPVE Freescale Semiconductor, MC9S12E256VPVE Datasheet - Page 152

• Manufacturer Part Number: MC9S12E256VPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256VPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 3 Port Integration Module (PIM9E256V1)
3.3.6.3
Read: Anytime. Write: Anytime.
This register configures port pins PT[7:0] as either input or output.
If the TIM0(1) module is enabled, each port pin configured for output compare is forced to be an output
and the associated Data Direction Register bit has no effect. If the associated timer output compare is
disabled, the corresponding DDRTx bit reverts to control the I/O direction of the associated pin.
If the TIM0(1) module is enabled, each port pin configured as an input capture has the corresponding
DDRTx bit controlling the I/O direction of the associated pin.
3.3.6.4
Read: Anytime. Write: Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
152
DDRT[7:0]
RDRT[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
DDRT7
RDRT7
Data Direction Port T
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Reduced Drive Port T
0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
Port T Data Direction Register (DDRT)
Port T Reduced Drive Register (RDRT)
0
0
7
7
DDRT6
RDRT6
0
0
6
6
Figure 3-39. Port T Reduced Drive Register (RDRT)
Figure 3-38. Port T Data Direction Register (DDRT)
Table 3-27. DDRT Field Descriptions
Table 3-28. RDRT Field Descriptions
DDRT5
RDRT5
MC9S12E256 Data Sheet, Rev. 1.08
0
0
5
5
DDRT4
RDRT4
0
0
4
4
Description
Description
DDRT3
RDRT3
3
0
3
0
DDRT2
RDRT2
0
0
2
2
DDRT1
RDRT1
Freescale Semiconductor
0
0
1
1
DDRT0
RDRT0
0
0
0
0