MC9S12E256VPVE Freescale Semiconductor, MC9S12E256VPVE Datasheet - Page 161

• Manufacturer Part Number: MC9S12E256VPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256VPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.5
The reset values of all registers are given in the register description in
Register
All ports start up as general-purpose inputs on reset.
3.5.1
All registers including the data registers get set/reset asynchronously.
properties after reset initialization.
Freescale Semiconductor
P
Definition”.
Resets
Reset Initialization
BKGD pin
M[3,1:0]
M[7:4]
Port
AD
Q
A
B
E
K
P
S
U
T
External Bus
“Multiplexed
Chapter 18,
(MEBIV3)”
Direction
Interface
Refer to
Data
Input
Input
Input
Input
Input
Input
Input
Input
Table 3-37. Port Reset State Summary
MC9S12E256 Data Sheet, Rev. 1.08
Pull Mode
Pull Up
Pull Up
Pull Up
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Reset States
Refer to
Red. Drive
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Chapter 18, “Multiplexed External Bus
Interface (MEBIV3)”
Chapter 3 Port Integration Module (PIM9E256V1)
Table 3-37
Section 3.3, “Memory Map and
Wired-OR
Disabled
Disabled
Disabled
Mode
N/A
N/A
N/A
N/A
N/A
summarizes the port
Interrupt
Disabled
N/A
N/A
N/A
N/A
N/A
N/A
N/A
161