MC9S12E256VPVE Freescale Semiconductor, MC9S12E256VPVE Datasheet - Page 135

IC MCU 256K FLASH 25MHZ 112-LQFP

MC9S12E256VPVE

Manufacturer Part Number
MC9S12E256VPVE
Description
IC MCU 256K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12E256VPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12E256VPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
3.3.1.8
Read: Anytime. Write: Anytime.
Each flag is set by an active edge on the associated input pin. The active edge could be rising or falling
based on the state of the corresponding PPSADx bit. To clear each flag, write “1” to the corresponding
PIFADx bit. Writing a “0” has no effect.
Freescale Semiconductor
PIFAD[15:0]
Reset
Reset
Field
15:0
W
W
R
R
PIFAD15
PIFAD7
Interrupt Flags Port AD
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Port AD Interrupt Flag Register (PIFAD)
0
0
7
7
Writing a “1” clears the associated flag.
If the ATDDIEN0(1) bit of the associated pin is set to 0 (digital input buffer
is disabled), active edges can not be detected.
PIFAD14
PIFAD6
0
0
6
6
Figure 3-9. Port AD Interrupt Flag Register (PIFAD)
PIFAD13
Table 3-8. PIFAD Field Descriptions
PIFAD5
MC9S12E256 Data Sheet, Rev. 1.08
0
0
5
5
PIFAD12
PIFAD4
NOTE
0
0
4
4
Description
PIFAD11
PIFAD3
3
0
3
0
Chapter 3 Port Integration Module (PIM9E256V1)
PIFAD10
PIFAD2
0
0
2
2
PIFAD9
PIFAD1
0
0
1
1
PIFAD8
PIFAD0
0
0
0
0
135

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