MC9S12E256VPVE Freescale Semiconductor, MC9S12E256VPVE Datasheet - Page 454

• Manufacturer Part Number: MC9S12E256VPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256VPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 15 Background Debug Module (BDMV4)
When BDM is activated, the CPU finishes executing the current instruction and then begins executing the
firmware in the standard BDM firmware lookup table. When BDM is activated by the breakpoint
sub-block, the type of breakpoint used determines if BDM becomes active before or after execution of the
next instruction.
In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses
0xFF00 to 0xFFFF. BDM registers are mapped to addresses 0xFF00 to 0xFF07. The BDM uses these
registers which are readable anytime by the BDM. However, these registers are not readable by user
programs.
15.4.3
Hardware commands are used to read and write target system memory locations and to enter active
background debug mode. Target system memory includes all memory that is accessible by the CPU such
as on-chip RAM, EEPROM, FLASH EEPROM, I/O and control registers, and all external memory.
Hardware commands are executed with minimal or no CPU intervention and do not require the system to
be in active BDM for execution, although they can continue to be executed in this mode. When executing
a hardware command, the BDM sub-block waits for a free CPU bus cycle so that the background access
does not disturb the running application program. If a free cycle is not found within 128 clock cycles, the
CPU is momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the
operation does not intrude on normal CPU operation provided that it can be completed in a single cycle.
However, if an operation requires multiple cycles the CPU is frozen until the operation is complete, even
though the BDM found a free cycle.
The BDM hardware commands are listed in
454
BACKGROUND
ACK_ENABLE
ACK_DISABLE
READ_BD_BYTE
READ_BD_WORD
READ_BYTE
Command
BDM Hardware Commands
If an attempt is made to activate BDM before being enabled, the CPU
resumes normal instruction execution after a brief delay. If BDM is not
enabled, any hardware BACKGROUND commands issued are ignored by
the BDM and the CPU is not delayed.
Opcode
(hex)
EC
D5
D6
E4
E0
90
16-bit address
16-bit data out
16-bit address
16-bit data out
16-bit address
16-bit data out
None
None
None
Data
Table 15-5. Hardware Commands
MC9S12E256 Data Sheet, Rev. 1.08
Table
Enter background mode if firmware is enabled. If enabled, an ACK will
be issued when the part enters active background mode.
Enable handshake. Issues an ACK pulse after the command is
executed.
Disable handshake. This command does not issue an ACK pulse.
Read from memory with standard BDM firmware lookup table in map.
Odd address data on low byte; even address data on high byte.
Read from memory with standard BDM firmware lookup table in map.
Must be aligned access.
Read from memory with standard BDM firmware lookup table out of
map. Odd address data on low byte; even address data on high byte.
NOTE
15-5.
Description
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