MC9S12E256VPVE Freescale Semiconductor, MC9S12E256VPVE Datasheet - Page 518

• Manufacturer Part Number: MC9S12E256VPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256VPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 18 Multiplexed External Bus Interface (MEBIV3)
18.3.2.3
Read: Anytime when register is in the map
Write: Anytime when register is in the map
This register controls the data direction for port A. When port A is operating as a general-purpose I/O port,
DDRA determines the primary direction for each port A pin. A 1 causes the associated port pin to be an
output and a 0 causes the associated pin to be a high-impedance input. The value in a DDR bit also affects
the source of data for reads of the corresponding PORTA register. If the DDR bit is 0 (input) the buffered
pin input state is read. If the DDR bit is 1 (output) the associated port data register bit state is read.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally. It is reset to 0x00 so the DDR does not override the three-state control
signals.
518
Reset
DDRA
Field
7:0
W
R
Bit 7
Data Direction Port A
0 Configure the corresponding I/O pin as an input
1 Configure the corresponding I/O pin as an output
Data Direction Register A (DDRA)
0
7
6
0
6
Figure 18-5. Data Direction Register A (DDRA)
Table 18-3. DDRA Field Descriptions
MC9S12E256 Data Sheet, Rev. 1.08
5
0
5
4
0
4
Description
3
3
0
2
0
2
Freescale Semiconductor
1
0
1
Bit 0
0
0