MC9S12E256VPVE Freescale Semiconductor, MC9S12E256VPVE Datasheet - Page 131

• Manufacturer Part Number: MC9S12E256VPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256VPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.3.1.2
Read: Anytime. Write: Never; writes to these registers have no effect.
If the ATDDIEN0(1) bit of the associated I/O pin is set to 0 (digital input buffer is disabled), a read returns
a 1. If the ATDDIEN0(1) bit of the associated I/O pin is set to 1 (digital input buffer is enabled), a read
returns the status of the associated pin.
3.3.1.3
Read: Anytime. Write: Anytime.
This register configures port pins PAD[15:0] as either input or output.
If a data direction bit is 0 (pin configured as input), then a read value on PTADx depends on the associated
ATDDIEN0(1) bit. If the associated ATDDIEN0(1) bit is set to 1 (digital input buffer is enabled), a read
on PTADx returns the value on port AD pin. If the associated ATDDIEN0(1) bit is set to 0 (digital input
buffer is disabled), a read on PTADx returns a 1.
Freescale Semiconductor
DDRAD[15:0]
Reset
Reset
Reset
Reset
Field
15:0
W
W
W
W
R
R
R
R
DDRAD15
PTIAD15
DDRAD7
PTIAD7
Port AD Input Register (PTIAD)
Port AD Data Direction Register (DDRAD)
Data Direction Port AD
0 Associated pin is configured as input.
1 Associated pin is configured as output.
1
1
0
0
7
7
7
7
= Reserved or Unimplemented
DDRAD14
DDRAD6
PTIAD14
PTIAD6
1
1
0
0
6
6
6
6
Figure 3-4. Port AD Data Direction Register (DDRAD)
Figure 3-3. Port AD Input Register (PTIAD)
DDRAD13
Table 3-3. DDRAD Field Descriptions
DDRAD5
PTIAD13
PTIAD5
MC9S12E256 Data Sheet, Rev. 1.08
1
1
0
0
5
5
5
5
DDRAD12
PTIAD12
DDRAD4
PTIAD4
1
1
0
0
4
4
4
4
Description
DDRAD11
PTIAD11
DDRAD3
PTIAD3
3
1
3
1
3
0
3
0
Chapter 3 Port Integration Module (PIM9E256V1)
DDRAD10
DDRAD2
PTIAD10
PTIAD2
1
1
0
0
2
2
2
2
DDRAD9
DDRAD1
PTIAD9
PTIAD1
1
1
0
0
1
1
1
1
DDRAD8
DDRAD0
PTIAD8
PTIAD0
1
1
0
0
0
0
0
0
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