MC9S12E256VPVE Freescale Semiconductor, MC9S12E256VPVE Datasheet - Page 550

• Manufacturer Part Number: MC9S12E256VPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256VPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 19 Module Mapping Control (MMCV4)
1
2
19.3.2.8
Read: Anytime
Write: Writes have no effect
Reset: Defined at chip integration, see
(MC9S12E256DGV1)”.
The MEMSIZ1 register reflects the state of the FLASH or ROM physical memory space and paging
switches at the core boundary which are configured at system integration. This register allows read
visibility to the state of these switches.
550
ROM_SW[1:0]
PAG_SW[1:0]
The RAM Reset BASE Address is based on the reset value of the INITRM register, 0x0009.
Alignment of the Allocated RAM space within the RAM mappable region is dependent on the value of RAMHAL.
Reset
ram_sw2:ram_sw0
Field
7:6
1:0
W
R ROM_SW1
100
101
110
111
Memory Size Register 1 (MEMSIZ1)
—
Allocated System FLASH or ROM Physical Memory Space — The allocated system FLASH or ROM
physical memory space is as given in
Allocated Off-Chip FLASH or ROM Memory Space — The allocated off-chip FLASH or ROM memory space
size is as given in
7
As stated, the bits in this register provide read visibility to the system
physical memory space allocations defined at system integration. The actual
array size for any given type of memory block may differ from the allocated
size. Please refer to
(MC9S12E256DGV1)”
= Unimplemented or Reserved
ROM_SW0
—
Table 19-9. Allocated RAM Memory Space (continued)
6
RAM Space
Figure 19-10. Memory Size Register 1 (MEMSIZ1)
Allocated
10K bytes
12K bytes
14K bytes
16K bytes
Table
Table 19-10. MEMSIZ1 Field Descriptions
19-12.
Chapter 1, “MC9S12E256 Device Overview
MC9S12E256 Data Sheet, Rev. 1.08
—
0
5
Chapter 1, “MC9S12E256 Device Overview
for actual sizes.
Mappable Region
Table
16K bytes
16K bytes
16K bytes
16K bytes
NOTE
—
0
4
19-11.
RAM
Description
2
2
2
—
3
0
RAM[15:14]
RAM[15:14]
RAM[15:14]
RAM[15:14]
Bits Used
INITRM
—
0
2
PAG_SW1
Freescale Semiconductor
—
1
Base Address
RAM Reset
0x1800
0x1000
0x0800
0x0000
PAG_SW0
—
0
1