MC9S12E256VPVE Freescale Semiconductor, MC9S12E256VPVE Datasheet - Page 136

• Manufacturer Part Number: MC9S12E256VPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256VPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 3 Port Integration Module (PIM9E256V1)
3.3.2
Port M is associated with the serial communication interface (SCI2) , Inter-IC bus (IIC) and the digital to
analog converter (DAC0 and DAC1) modules. Each pin is assigned to these modules according to the
following priority: IIC/SCI2/DAC1/DAC0 > general-purpose I/O.
When the IIC bus is enabled, the PM[7:6] pins become SCL and SDA respectively. Refer to
“Inter-Integrated Circuit (IICV2)”
When the SCI2 receiver and transmitter are enabled, the PM[5:4] become RXD2 and TXD2 respectively.
Refer to
the SCI receiver and transmitter.
When the DAC1 and DAC0 outputs are enabled, the PM[1:0] become DAO1 and DAO0 respectively.
Refer to
disabling the DAC output.
During reset, PM[3] and PM[1:0] pins are configured as high-impedance inputs and PM[7:4] pins are
configured as pull-up inputs.
3.3.2.1
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRMx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRMx) is set to 0 (input), a read returns the value of the pin.
136
DAC1/DAC0:
Reset
SCI2:
IIC:
Chapter 8, “Serial Communication Interface (SCIV4)”
Chapter 7, “Digital-to-Analog Converter (DAC8B1CV1)”
W
R
Port M
Port M I/O Register (PTM)
PTM7
SCL
0
7
= Reserved or Unimplemented
PTM6
SDA
0
6
Figure 3-10. Port M I/O Register (PTM)
for information on enabling and disabling the IIC bus.
MC9S12E256 Data Sheet, Rev. 1.08
PTM5
TXD2
0
5
PTM4
RXD2
0
4
PTM3
for information on enabling and disabling
0
3
for information on enabling and
0
0
2
Freescale Semiconductor
PTM1
DAO1
0
1
Chapter 10,
PTM0
DAO0
0
0