ST7FMC2R6T6 STMicroelectronics, ST7FMC2R6T6 Datasheet - Page 103

• Manufacturer Part Number: ST7FMC2R6T6
• Description: MCU 8BIT 32K FLASH 64TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FMC2R6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ST7FMC2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MC-KIT/BLDC, ST7MDT50-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-6408 - BOARD EVAL BLDC SENSORLESS MOTOR497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4868

SERIAL PERIPHERAL INTERFACE (cont’d)
10.4.6 Low Power Modes
10.4.6.1 Using the SPI to wake up the device
from Halt mode
In slave configuration, the SPI is able to wake up
the device from Halt mode through a SPIF inter-
rupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
Mode
Wait
Halt
No effect on SPI.
SPI interrupt events cause the device to exit
from Wait mode.
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI opera-
tion resumes when the device is woken up by
an interrupt with “exit from Halt mode” capa-
bility. The data received is subsequently read
from the SPIDR register when the software is
running (interrupt vector fetching). If several
data are received before the wake-up event,
then an overrun error is generated. This error
can be detected after the fetch of the inter-
rupt routine that woke up the Device.
Description
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
Caution: The SPI can wake up the device from
Halt mode only if the Slave Select signal (external
SS pin or the SSI bit in the SPICSR register) is low
when the device enters Halt mode. So, if Slave se-
lection is configured as external (see
10.4.3.2), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
10.4.7 Interrupts
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
SPI End of
Transfer Event
Master Mode
Fault Event
Overrun Error
Interrupt Event
MODF
Event
SPIF
OVR
Flag
ST7MC1xx/ST7MC2xx
Control
Enable
SPIE
Bit
from
Wait
Exit
Yes
Section
103/309
from
Exit
Halt
Yes
No
1