ST7FMC2R6T6 STMicroelectronics, ST7FMC2R6T6 Datasheet - Page 36

• Manufacturer Part Number: ST7FMC2R6T6
• Description: MCU 8BIT 32K FLASH 64TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FMC2R6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ST7FMC2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MC-KIT/BLDC, ST7MDT50-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-6408 - BOARD EVAL BLDC SENSORLESS MOTOR497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4868

ST7MC1xx/ST7MC2xx
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 1)
Reset Value: 00000000 (00h)
Bit 7 = PAGE SICSR Register Page Selection
This bit selects the SICSR register page. It is set
and cleared by software
0: Access to SICSR register mapped in page 0.
1: Access to SICSR register mapped in page 1.
Bit 6 = Reserved, must be kept cleared.
Bit 5 = VCOEN VCO Enable
This bit is set and cleared by software.
0: VCO (Voltage Controlled Oscillator) connected
1: VCO tied to ground in order to obtain a 10-MHz
Notes:
1. During ICC session, this bit is set to 1 in order to
have an internal frequency which does not depend
on the input clock. Then, it can be reset in order to
run faster with an external oscillator.
Bit 4 = LOCK PLL Locked
This bit is read only. It is set by hardware. It is set
automatically when the PLL reaches its operating
frequency.
0: PLL not locked
1: PLL locked
36/309
1
GE
PA
to the output of the PLL charge pump (default
mode), to obtain a 16-MHz output frequency
(with an 8-MHz input frequency).
frequency (f
7
0
VCO
vco
EN
)
CK
LO
PLL
EN
0
SEL
CK-
0
0
Bit 3 = PLLEN PLL Enable
This bit enables the PLL and the clock detector. It
is set and cleared by software.
0: PLL and Clock Detector (CKD) disabled
1: PLL and Clock Detector (CKD) enabled
Notes:
1. During ICC session, this bit is set to 1.
2. PLL cannot be disabled if PLL clock source is
selected (CKSEL= 1).
Bit 2 = Reserved, must be kept cleared.
Bit 1 = CKSEL Clock Source Selection
This bit selects the clock source: oscillator clock or
clock from the PLL. It is set and cleared by soft-
ware. It can also be set by option byte (PLL opt)
0: Oscillator clock selected
1: PLL clock selected
Notes:
1. During ICC session, this bit is set to 1. Then,
CKSEL can be reset in order to run with f
2. Clock from the PLL cannot be selected if the
PLL is disabled (PLLEN =0)
3. If the clock source is selected by PLL option bit,
CKSEL bit selection has no effect.
Bit 0 = Reserved, must be kept cleared.
OSC
.