ST7FMC2R6T6 STMicroelectronics, ST7FMC2R6T6 Datasheet - Page 210

• Manufacturer Part Number: ST7FMC2R6T6
• Description: MCU 8BIT 32K FLASH 64TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FMC2R6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ST7FMC2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MC-KIT/BLDC, ST7MDT50-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-6408 - BOARD EVAL BLDC SENSORLESS MOTOR497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4868

ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
CONTROL REGISTER A (MCRA)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = MOE: Output Enable bit.
0: Outputs disabled
1: Outputs enabled
Notes:
– The reset state is either high impedance, high or
– When the MOE bit in the MCRA register is reset
Bit 6 = CKE: Clock Enable Bit.
0: Motor Control peripheral Clocks disabled
1: Motor Control peripheral Clocks enabled
Note: Clocks disabled means that all peripheral in-
ternal clocks (Delay manager, internal sampling
clock, PWM generator) are disabled. Therefore,
the peripheral can no longer detect events and the
preload registers do not operate.
When Clocks are disabled, write accesses are al-
lowed, so for example, MTIM counter register can
be reset by software.
210/309
1
MOE
low state depending on the corresponding option
bit.
(MCOx outputs in reset state), and the SR bit in
the MCRA register is reset (sensorless mode)
and the SPLG bit in the MCRC register is reset
(sampling at PWM frequency) then, depending
on the state of the ZSV bit in the MSCR register,
Z event sampling can run or be stopped (and D
event is sampled).
7
CKE
6
MOE bit
0
1
SR
5
DAC
4
V0C1
3
MCO[5:0] Output pin
Output enabled
SWA
Reset state
2
State
PZ
1
DCB
0
Table 56. Output configuration summary
Note 1: “Peripheral frozen” configuration is not
recommended, as the peripheral may be stopped
in a unknown state (depending on PWM generator
outputs,etc.). It is better practice to exit from run
mode by first setting output state (by toggling ei-
ther MOE or DAC bits) and then to disabling the
clock if needed.
Note 2: In Direct Access Mode (DAC=1), when
CKE=0 (Peripheral Clock disabled) only logical
level can be applied on the MCOx outputs when
they are enabled whereas when CKE=1 (Peripher-
al Clock enabled), a PWM signal can be applied
on them. Refer to
set-up,” on page 221
Note 3: When clocks are disabled (CKE bit reset)
while outputs are enabled (MOE bit set), the ef-
fects on the MCOx outputs where PWM signal is
applied depend on the running mode selected:
– in voltage mode (VOC1 bit=0), the MCOx out-
– in current mode (VOC1 bit=1), the MCOx outputs
In all cases, MCOx outputs where a level 1 was
applied before disabling the clocks stay at level 1.
That is why it is recommended to disable the
MCOx outputs (reset MOE bit) before disabling the
clocks. This will put all the MCOx outputs under re-
set state defined by the corresponding option bit.
CKE
bit
puts where PWM signal is applied stay at level 1.
where PWM signal is applied are put to level 0.
0
0
0
1
1
1
MOE
bit
0
1
1
0
1
1
DAC
bit
0
1
0
1
x
x
Peripheral
Table 74, “DeadTime generator
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Clock
Peripheral frozen (see
MPHST (PWM can be
(only logical level)
Direct access via
Direct access via
Effect on MCOx
running mode.
note 1 below)
Reset state
Reset state
Standard
applied)
MPHST
Output