ST7FMC2R6T6 STMicroelectronics, ST7FMC2R6T6 Datasheet - Page 152

• Manufacturer Part Number: ST7FMC2R6T6
• Description: MCU 8BIT 32K FLASH 64TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FMC2R6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ST7FMC2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MC-KIT/BLDC, ST7MDT50-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-6408 - BOARD EVAL BLDC SENSORLESS MOTOR497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4868

ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Table 30
ZVD and CPB bits. In most cases, the D and Z
events have opposite edge polarity, so the ZVD bit
is usually 0.
Table 30. ZVD and CPB Edge Selection Bits
Legend:
DWF= D window filter
DEF= D event filter
ZWF = Z window filter
ZEF = Z event filter
Refer also to
152/309
1
ZVD bit
0
0
1
1
shows the event control selected by the
Table 34 on page
Note: The ZVD bit is located in the MPOL register, the CPB bit is in the MCRB register.
CPB bit
0
1
0
1
162.
C
C
C
C
DWF
DWF
DWF
DWF
DEF
DEF
DEF
DEF
Event generation vs input data sampled
ZWF
ZWF
ZWF
ZWF
D
D
D
D
H
H
H
H
ZEF
ZEF
Z
Z
ZEF
ZEF
Z
Z