ST7FMC2R6T6 STMicroelectronics, ST7FMC2R6T6 Datasheet - Page 206

• Manufacturer Part Number: ST7FMC2R6T6
• Description: MCU 8BIT 32K FLASH 64TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FMC2R6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ST7FMC2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MC-KIT/BLDC, ST7MDT50-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-6408 - BOARD EVAL BLDC SENSORLESS MOTOR497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4868

ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.10.7 Timer Re-synchronisation
The 12-bit timer can be re-synchronized by a sim-
ple write access with FFh value in the MISR regis-
ter. Re-synchronization means that the 12-bit
counter is reset and all the compare preload regis-
ters MCP0, MCPU, MCPV, MCPW are transferred
to the active registers.
To re-synchronize the 12-bit timer properly , the
following procedure must be applied:
– 1. Load the new values in the preload compare
– 2. Load FFh value in the MISR register (this will
– 3. Reset the PUI flag by loading 7Fh in the MISR
Note: Loading FFh value in the MISR register will
have no effect on any other flag than the PUI flag
and will generate a PWM update interrupt if the
PUM bit is set.
Warning: In switched mode (SWA bit is reset), the
procedure is the same and loading FFh in the
MISR register will have no effect on flags except
on the PUI flag. As a consequence, it is recom-
mended to avoid setting RMI and RPI flags at the
same time in switched mode because none of
them will be taken into account.
10.6.10.8 PWM generator initialization and
start-up
The three-phase generator counter stays in reset
state (i.e. stopped and equal to 0), as long as MTC
peripheral clock is disabled (CKE = 0).
Setting the CKE bit has two actions on the PWM
generator:
■
■
206/309
1
registers
reset the counter and transfer the compare
preload registers in the active registers: U event)
register. Refer to Note 2 on
It starts the PWM counter
It forces the update of all registers with preload
registers transferred on U update event, i.e.
MREP, MPCR, MCMP0, MCMPU, MCMPV,
MCMPW (in 12-bit mode, both MCMPxL and
page 209
10.6.11 Low Power Modes
Before executing a HALT or WFI instruction, soft-
ware must stop the motor, and may choose to put
the outputs in high impedance.
10.6.12 Interrupts
The MTC interrupt events are connected to the
three interrupt vectors (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
Mode
Wait
Halt
Ratio increment
Ratio decrement
Speed Error
Emergency Stop
Current Limitation
BEMF Zero-Crossing
End of Demagnetization
Commutation or
Capture
PWM Update
Sampling Out
MCMPxH must have been written, following the
mandatory LSB/MSB sequence, before setting
CKE bit). It consequently generates a U
interrupt.
Interrupt Event
Description
No effect on MTC interface.
MTC interrupts exit from Wait mode.
MTC registers are frozen.
In Halt mode, the MTC interface is in-
active. The MTC interface becomes
operational again when the MCU is
woken up by an interrupt with “exit
from Halt mode” capability.
Event
RPI
RMI
SEI
EI
CLI
ZI
DI
CI
PUI
SOI
Flag
Control
RIM
SEM
EIM
CLIM
ZIM
DIM
CIM
PUM
SOM
Enable
Bit
from
Wait
Exit
Yes No
Yes No
Yes No
Yes No
Yes No
Yes No
Yes No
Yes No
Yes No
Yes Not
from
Exit
Halt