ST7FMC2R6T6 STMicroelectronics, ST7FMC2R6T6 Datasheet - Page 176

MCU 8BIT 32K FLASH 64TQFP

ST7FMC2R6T6

Manufacturer Part Number
ST7FMC2R6T6
Description
MCU 8BIT 32K FLASH 64TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FMC2R6T6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
LINSCI, SPI
Peripherals
LVD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ST7FMC2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
60
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MC-KIT/BLDC, ST7MDT50-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-6408 - BOARD EVAL BLDC SENSORLESS MOTOR497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-4868

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FMC2R6T6
Manufacturer:
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Quantity:
10 000
Part Number:
ST7FMC2R6T6
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0
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
When using hardware commutation C
quence of events needed is C
Z events and the value written in the registers are
checked at different times.
If SDM bit is set, meaning simulated demagnetisa-
tion, a value must be written in the MDREG regis-
ter to generate the simulated demagnetisation.
This value must be written after the C (either C
C
tion.
If SZ bit is set, meaning simulated zero-crossing
event, a value must be written in the MZREG reg-
ister to generate the simulated zero-crossing. This
value must be written after the D event (D
preceding the simulated zero-crossing.
When using simulated commutation (C
sult of the 8*8 hardware multiplication of the delay
manager is not taken in account and must be over-
written if the SC bit has been set in a Z event inter-
rupt and the sequence of events is broken mean-
ing that several consecutive simulated commuta-
tions can be implemented.
As soon as the SC bit is set in the MCRC register,
the system won’t necessarily expect a D event af-
ter a C event. This can be used for an application
in sensor mode with only one Hall Effect sensor for
example.
Be careful that the D and Z events are not ignored
by the peripheral, this means that for example if a
176/309
1
H
) event preceding the simulated demagnetisa-
H
then D and finally
H
S
, the se-
), the re-
H
or D
s
or
S
)
Z event occurs, the MTIM timer is reset. In Simu-
lated Commutation mode, the sequence D -> Z is
expected, and this order must be repected.
As the sequence of events may not be the same
when using simulated commutation, as soon as
the SC bit is set, the capture/compare feature and
protection on MCOMP register is reestablished
only after a write to the MCOMP register. This
means that as soon as the SC bit is set, if no write
access is done to the MCOMP register, no com-
mutation event will be generated, whatever the
value of MCOMP compared to MTIM at the time
SC is set. This does not depend on the running
mode: switched or autoswitched mode (SWA bit).
If software commutation event is used with a nor-
mal sequence of events C-->D-->Z, it is recom-
mended to write the MCOMP register during the Z
interrupt routine to avoid any spurious comparison
as several consecutive C
ed.
Note that two different simulated events can be
used in the same step (like D
Note also that for more precision, it is recommend-
ed to use the value captured from the preceding
hardware event to compute the value used to gen-
erate simulated events.
Figure
of simulated event generation.
95,
Figure 96
and
s
Figure 97
events can be generat-
S
followed by Z
shows details
S
).

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