ST7FMC2R6T6 STMicroelectronics, ST7FMC2R6T6 Datasheet - Page 300

• Manufacturer Part Number: ST7FMC2R6T6
• Description: MCU 8BIT 32K FLASH 64TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FMC2R6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ST7FMC2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MC-KIT/BLDC, ST7MDT50-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-6408 - BOARD EVAL BLDC SENSORLESS MOTOR497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4868

ST7MC1xx/ST7MC2xx
IMPORTANT NOTES (Cont’d)
15.2 CLEARING ACTIVE INTERRUPTS OUTSIDE
INTERRUPT ROUTINE
When an active interrupt request occurs at the
same time as the related flag or interrupt mask is
being cleared, the CC register may be corrupted.
Concurrent interrupt context
The symptom does not occur when the interrupts
are handled normally, i.e. when:
- The interrupt request is cleared (flag reset or in-
terrupt mask) within its own interrupt routine
- The interrupt request is cleared (flag reset or in-
terrupt mask) within any interrupt routine
- The interrupt request is cleared (flag reset or in-
terrupt mask) in any part of the code while this in-
terrupt is disabled
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
Perform SIM and RIM operation before and after
resetting an active interrupt request
Nested interrupt context
The symptom does not occur when the interrupts
are handled normally, i.e. when:
- The interrupt request is cleared (flag reset or in-
terrupt mask) within its own interrupt routine
- The interrupt request is cleared (flag reset or in-
terrupt mask) within any interrupt routine with high-
er or identical priority level
- The interrupt request is cleared (flag reset or in-
terrupt mask) in any part of the code while this in-
terrupt is disabled
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
300/309
Ex:
SIM
reset flag or interrupt mask
RIM
PUSH CC
SIM
reset flag or interrupt mask
POP CC
15.3 TIMD SET SIMULTANEOUSLY WITH OC
INTERRUPT
If the 16-bit timer is disabled at the same time as
the output compare event occurs then the output
compare flag gets locked and cannot be cleared
before the timer is enabled again.
15.3.1 Impact on the application
If the output compare interrupt is enabled, then the
output compare flag cannot be cleared in the timer
interrupt routine. Consequently the interrupt serv-
ice routine is called repeatedly and the application
gets stuck which causes the watchdog reset if en-
abled by the application.
15.3.2 Workaround
Disable the timer interrupt before disabling the tim-
er. While enabling, first enable the timer, then en-
able the timer interrupts.
Perform the following to disable the timer
– TACR1 or TBCR1 = 0x00h; // Disable the com-
– TACSR | or TBCSR |= 0x40; // Disable the timer.
– Perform the following to enable the timer again
– TACSR & or TBCSR & = ~0x40; // Enable the
– TACR1 or TBCR1 = 0x40; // Enable the compare
15.4 LINSCI LIMITATIONS
15.4.1 LINSCI wrong break duration
SCI Mode
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected:
- 20 bits instead of 10 bits if M=0
- 22 bits instead of 11 bits if M=1.
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than expect-
ed.
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen-
cy of 19200 baud (fCPU=8MHz and SCI-
BRR=0xC9), the wrong break duration occurrence
is around 1%.
pare interrupt.
timer.
interrupt.