ST7FMC2R6T6 STMicroelectronics, ST7FMC2R6T6 Datasheet - Page 52

• Manufacturer Part Number: ST7FMC2R6T6
• Description: MCU 8BIT 32K FLASH 64TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FMC2R6T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ST7FMC2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MC-KIT/BLDC, ST7MDT50-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-6408 - BOARD EVAL BLDC SENSORLESS MOTOR497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4868

ST7MC1xx/ST7MC2xx
POWER SAVING MODES (Cont’d)
8.4 ACTIVE-HALT AND HALT MODES
Active-halt and Halt modes are the two lowest
power consumption modes of the MCU. They are
both entered by executing the ‘HALT’ instruction.
The decision to enter either in Active-halt or Halt
mode is given by the MCC/RTC interrupt enable
flag (OIE bit in MCCSR register).
8.4.1 ACTIVE-HALT MODE
Active-halt mode is the lowest power consumption
mode of the MCU with a real-time clock available.
It is entered by executing the ‘HALT’ instruction
when the OIE bit of the Main Clock Controller Sta-
tus register (MCCSR) is set (see
page 37
The MCU can exit Active-halt mode on reception
of either an MCC/RTC interrupt, a specific inter-
rupt (see Table 8, “Interrupt Mapping,” on
page 44) or a RESET. When exiting Active-halt
mode by means of an interrupt, no 256 or 4096
CPU cycle delay occurs. The CPU resumes oper-
ation by servicing the interrupt or by fetching the
reset vector which woke it up (see
When entering Active-halt mode, the I[1:0] bits in
the CC register are forced to ‘10b’ to enable inter-
rupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
In Active-halt mode, only the main oscillator and its
associated counter (MCC/RTC) are running to
keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as ex-
ternal or auxiliary oscillator).
The safeguard against staying locked in Active-
halt mode is provided by the oscillator interrupt.
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering Active-halt mode while the Watchdog is
active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
52/309
1
MCCSR
OIE bit
0
1
for more details on the MCCSR register).
Halt mode
Active-halt mode
Power Saving Mode entered when HALT
instruction is executed
Figure
section 6.4 on
29).
Figure 28. Active-halt Timing Overview
Figure 29. Active-halt Mode Flow-chart
Notes:
1. This delay occurs only if the MCU exits Active-
halt mode by means of a RESET.
2. Peripheral clocked with an external clock source
can still be active.
3. Only the MCC/RTC interrupt and some specific
interrupts can exit the MCU from Active-halt mode
(such as external interrupt). Refer to Table 8, “In-
terrupt Mapping,” on page 44 for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
[MCCSR.OIE=1]
INSTRUCTION
HALT INSTRUCTION
RUN
N
(MCCSR.OIE=1)
HALT
INTERRUPT
ACTIVE
HALT
Y
256 OR 4096 CPU
CYCLE DELAY
INTERRUPT
3)
RESET
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
FETCH RESET VECTOR
OR
OSCILLATOR
PERIPHERALS
OSCILLATOR
PERIPHERALS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
CPU
I[1:0] BITS
CPU
I[1:0] BITS
N
CYCLE DELAY
RESET
Y
1)
VECTOR
FETCH
RUN
2)
XX
XX
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
10
4)
4)