UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 101

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address
FFF00H
FFF01H
FFF02H
FFF03H
FFF04H
FFF05H
FFF06H
FFF07H
FFF08H
FFF09H
FFF0AH
FFF0BH
FFF0CH Port register 12
FFF0DH Port register 13
FFF0EH
FFF0FH
FFF10H
FFF11H
FFF12H
FFF13H
FFF14H
FFF15H
FFF16H
FFF17H
FFF18H
FFF19H
FFF1AH
FFF1BH
FFF1EH
FFF1FH
FFF20H
FFF21H
FFF22H
FFF23H
FFF24H
FFF25H
FFF26H
FFF27H
Port register 0
Port register 1
Port register 2
Port register 3
Port register 4
Port register 5
Port register 6
Port register 7
Port register 8
Port register 9
Port register 10
Port register 11
Port register 14
Port register 15
Serial data register 00
Serial data register 01
Serial data register 12
Serial data register 13
Timer data register 00
Timer data register 01
12-bit A/D conversion result register
Port mode register 0
Port mode register 1
Port mode register 2
Port mode register 3
Port mode register 4
Port mode register 5
Port mode register 6
Port mode register 7
Special Function Register (SFR) Name
8-bit A/D conversion result register ADCRH
Table 3-5. SFR List (1/5)
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
TXD0/
SIO00
RXD0/
SIO01
TXD3
RXD3
TDR00
TDR01
ADCR
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
−
−
−
−
Symbol
SDR00
SDR01
SDR12
SDR13
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
1-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
−
−
√
√
√
√
√
√
√
√
Manipulable Bit
CHAPTER 3 CPU ARCHITECTURE
Range
8-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
−
√
−
√
−
−
−
−
√
√
√
√
√
√
√
√
√
16-bit
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
After Reset
Undefined
0000H
0000H
0000H
0000H
0000H
0000H
0000H
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
−
−
−
−
−
−
√
√
√
√
√
√
−
−
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
101