UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 245

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(2) Example of setting procedure when using the subsystem clock as the CPU clock
(3) Example of setting procedure when stopping the subsystem clock
<3> Waiting for the stabilization of the subsystem clock oscillation
Caution The CMC register can be written only once after reset release, by an 8-bit memory manipulation
<1> Setting subsystem clock oscillation
<2> Setting the subsystem clock as the source clock of the CPU/peripheral hardware clock and setting the
Caution When the subsystem clock is used as the CPU clock, the subsystem clock is also supplied to the
<1> Confirming the CPU clock status (CKC register)
<2> Stopping the subsystem clock (CSC register)
Cautions 1. Be sure to confirm that CLS = 0 when setting XTSTOP to 1. In addition, stop the peripheral
Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function.
(See 5.6.3 (1) Example of setting procedure when oscillating the subsystem clock.)
Note The setting of <1> is not necessary when while the subsystem clock is operating.
division ratio of the set clock (CKC register)
When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to the internal high-
speed oscillation clock or high-speed system clock.
When XTSTOP is set to 1, subsystem clock is stopped.
CSS
CLS
Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock.
instruction.
Therefore, it is necessary to also set the value of the EXCLK and OSCSEL bits at the same time.
For EXCLK and OSCSEL bits, see 5.6.1 (1) Example of setting procedure when oscillating the X1
clock or 5.6.1 (2) Example of setting procedure when using the external main system clock.
peripheral hardware (except the real-time counter, timer array unit (when f
edge of TI0mn input, or the valid edge of INTRTCI is selected as the count clock), clock
output/buzzer output, and watchdog timer). At this time, the operations of the A/D converter and
IICA are not guaranteed. For the operating characteristics of the peripheral hardware, refer to the
chapters describing the various peripheral hardware as well as CHAPTER 31 ELECTRICAL
SPECIFICATIONS.
0
0
1
1
2. The subsystem clock oscillation cannot be stopped using the STOP instruction.
hardware if it is operating on the subsystem clock.
SDIV
MCS
0
1
×
0
1
Internal high-speed oscillation clock or 20 MHz internal high-speed
oscillation clock
High-speed system clock
Subsystem clock
f
f
SUB
SUB
/2
Note
Selection of CPU/Peripheral Hardware Clock (f
CPU Clock Status
CHAPTER 5 CLOCK GENERATOR
CLK
)
SUB
/2, f
SUB
/4, the valid
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