UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 288

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
• 78K0R/LF3
• 78K0R/LG3
• 78K0R/LH3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: F01BCH, F01BDH
Address: F01BCH, F01BDH
Address: F01BCH, F01BDH
Address: F01E4H, F01E5H
(11) Timer output level register p (TOLp)
Symbol
Symbol
Symbol
Symbol
TOL0
TOL0
TOL0
TOL1
TOLp is a register that controls the timer output level of each channel.
The setting of the inverted output of channel q by this register is reflected at the timing of set or reset of the timer
output signal while the timer output is enabled (TOEpq = 1) in the combination operation mode (TOMpq = 1). In
the toggle mode (TOMpq = 0), this register setting is invalid.
TOLp can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TOLp can be set with an 8-bit memory manipulation instruction with TOLpL.
Reset signal generation clears this register to 0000H.
Remarks 1. If the value of this register is rewritten during timer operation, the timer output is inverted when the
Cautions 1. For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TOL0 to “0”.
TOLpq
15
15
15
15
0
0
0
0
0
1
3. For 78K0R/LH3, be sure to clear bit 15 to 8 of TOL0, bits 15 to 4 of TOL1 to “0”.
2. For 78K0R/LG3, be sure to clear bits 15 to 8 of TOL0 to “0”.
2. pq: Unit number + Channel number (only for channels provided with timer I/O pins)
Positive logic output (active-high)
Inverted output (active-low)
14
14
14
14
timer output signal changes next, instead of immediately after the register value is rewritten.
78K0R/LF3: p = 0, pq = 00 to 04, 07
78K0R/LG3: p = 0, pq = 00 to 07
78K0R/LH3: p = 0, 1, pq = 00 to 07, 10 to 13
0
0
0
0
After reset: 0000H
13
13
13
13
Figure 6-20. Format of Timer Output Level Register p (TOLp)
After reset: 0000H
After reset: 0000H
After reset: 0000H
0
0
0
0
12
12
12
12
0
0
0
0
11
11
11
11
0
0
0
0
R/W
R/W
R/W
R/W
10
10
10
10
0
0
0
0
Control of timer output level of channel q
9
0
9
0
9
0
9
0
8
0
8
0
8
0
8
0
TOL
TOL
TOL
07
07
07
7
7
7
7
0
TOL
TOL
06
06
6
0
6
6
6
0
TOL
TOL
05
05
CHAPTER 6 TIMER ARRAY UNIT
5
0
5
5
5
0
TOL
TOL
TOL
04
04
04
4
4
4
4
0
TOL
TOL
TOL
TOL
03
03
03
13
3
3
3
3
TOL
TOL
TOL
TOL
02
02
02
12
2
2
2
2
TOL
TOL
TOL
TOL
01
01
01
11
1
1
1
1
TOL
TOL
TOL
TOL
00
00
00
10
0
0
0
0
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