UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 97

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
3.2.2 General-purpose registers
purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
BC, DE, and HL).
names (R0 to R7 and RP0 to RP3).
register bank configuration, an efficient program can be created by switching between a register for normal processing and
a register for interrupts for each bank.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The general-
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX,
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4-
Caution It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or as a stack area.
SP←SP−2
SP←SP−4
SP
SP−2
SP−1
SP
SP−4
SP−3
SP−2
SP−1
→
→
↑
↑
↑
CALL, CALLT instructions
↑
↑
↑
↑
↑
PUSH rp instruction
Register pair higher
Register pair lower
Figure 3-11. Data to Be Saved to Stack Memory
PC19 to PC16
(4-byte stack)
PC15 to PC8
PC7 to PC0
00H
SP←SP−2
SP←SP−4
SP
SP−2
SP−1
SP
SP−4
SP−3
SP−2
SP−1
→
↑
↑
↑
→
↑
↑
↑
↑
↑
Interrupt, BRK instruction
PUSH PSW instruction
CHAPTER 3 CPU ARCHITECTURE
PC19 to PC16
(4-byte stack)
PC15 to PC8
PC7 to PC0
PSW
PSW
00H
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