UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 611

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
15.5.9 Address match detection method
set to the slave address register (SVA) matches the slave address sent by the master device, or when an extension code
has been received.
15.5.10 Error detection
(IICA) of the transmitting device, so the IICA data prior to transmission can be compared with the transmitted IICA data to
enable detection of transmission errors. A transmission error is judged as having occurred when the compared data
values do not match.
15.5.11 Extension code
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
In I
Address match can be detected automatically by hardware. An interrupt request (INTIICA) occurs when the address
In I
(1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag (EXC)
(2) The settings below are specified if 11110xx0 is transferred from the master by using a 10-bit address transfer when
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code,
2
2
C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address.
C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by the IICA shift register
is set to 1 for extension code reception and an interrupt request (INTIICA) is issued at the falling edge of the eighth
clock. The local address stored in the slave address register (SVA) is not affected.
the SVA register is set to 11110xx0. Note that INTIICA occurs at the falling edge of the eighth clock.
• Higher four bits of data match: EXC = 1
• Seven bits of data match:
Remark
such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave device,
set bit 6 (LREL) of the IICA control register 0 (IICCTL0) to 1 to set the standby mode for the next communication
operation.
Remark
Slave Address
EXC:
COI:
For extension codes other than the above, refer to THE I
0 0 0 0 0 0 0
1 1 1 1 0 x x
1 1 1 1 0 x x
Bit 5 of IICA status register (IICS)
Bit 4 of IICA status register (IICS)
Table 15-3. Bit Definitions of Main Extension Code
R/W Bit
COI = 1
0
0
1
General call address
10-bit slave address specification (for address authentication)
after address match)
10-bit slave address specification (for read command issuance
CHAPTER 15 SERIAL INTERFACE IICA
2
Description
C-BUS SPECIFICATION published by NXP.
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