UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 235

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
<1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
<2> When the power supply voltage exceeds 1.61 V (TYP.), the reset is released and the internal high-speed
<3> The CPU starts operation on the internal high-speed oscillation clock
<4> Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 5.6.1 Example of controlling high-
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
Subsystem clock (f
oscillation clock (f
(when XT1 oscillation
(when X1 oscillation
Internal reset signal
Internal high-speed
oscillation clock (f
system clock (f
20 MHz internal
oscillator automatically starts oscillation.
for the voltage of the power supply or regulator to stabilize has been performed after reset release.
speed system clock and (1) in 5.6.3 Example of controlling subsystem clock).
switching via software (see (3) in 5.6.1 Example of controlling high-speed system clock and (2) in 5.6.3
Example of controlling subsystem clock).
Switch to the 20 MHz internal high-speed oscillation clock by setting the DSCON bit (bit 0 of the 20 MHz internal
high-speed oscillation control register (DSCCTL)), waiting for 100
using software
(Notes and Cautions are listed on the next page.)
Power supply
voltage (V
high-speed
High-speed
CPU clock
selected)
selected)
Figure 5-13. Clock Generator Operation When Power Supply Voltage Is Turned On
IH20
SUB
0 V
DD
MX
IH
)
)
)
)
)
(When LVI Default Start Function Stopped Is Set (Option Byte: LVIOFF = 1))
1.61 V
(TYP.)
Note 4
<1>
.
<2>
<3>
0.5 V/ms
Note 1
(MIN.)
1.8 V
Reset processing
(2.12 to 5.84 ms)
is set by software.
DSCON = 1
1 or 8 MHz internal high-
speed oscillation clock
<4>
20 MHz internal high-speed oscillation clock
oscillation stabilization time : 100 s
<5>
is specified by software.
speed oscillation clock
SELDSC = 1
20 MHz internal high-
Starting X1 oscillation
is specified by software.
Starting XT1 oscillation
<4>
μ
s, and then setting the SELDSC bit to 1 by
Note 3
μ
Switched by
CHAPTER 5 CLOCK GENERATOR
1 or 8 MHz internal high-
software
speed oscillation clock
<4>
after a reset processing such as waiting
X1 clock
oscillation stabilization time
<5>
system clock
High-speed
Note 2
<5>
Subsystem
clock
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