UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 797

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
Remarks 1.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
System clock
CPU
Flash memory
RAM
Port (latch)
Timer array unit (TAU)
Real-time counter (RTC)
Watchdog timer
Clock output/buzzer output
A/D converter
D/A converter
Operational amplifier
Voltage reference
Serial array unit (SAU)
Serial interface (IICA)
LCD controller/driver
Multiplier/divider
DMA controller
Power-on-clear function
Low-voltage detection function
External interrupt
Key interrupt
BCD correction circuit (BCD)
Main system clock
Subsystem clock
f
IL
2.
Item
f
f
f
The functions mounted depend on the product. Refer to 1.4
Functions.
IH
EX
IL
:
: Internal high-speed oscillation clock,
: External main system clock,
Internal low-speed oscillation clock
f
f
f
f
IH
X
EX
XT
Clock supply to the CPU is stopped.
Operation stopped
Operation stopped (X1 and X2 pins are input port mode)
Clock input invalid (pin is input port mode)
Operation stopped (XT1 and XT2 pins are input port mode)
Operation stopped
Operation stopped (The value, however, is retained when the voltage is at least the power-on-
clear detection voltage.)
Set P130 to low-level output. The port pins except for P130 become high impedance.
Operation stopped
Operation stopped
(COM only pin, SEG only pin, COM/SEG alternate pin: GND output, SEG/general-purpose port
alternate pin: input port, V
CAPL/P01 pin: input port)
Operation stopped
Detection operation possible
Operation stopped (however, operation continues at LVI reset)
Operation stopped
Table 22-1. Operation Statuses During Reset Period
LC0
to V
LC2
f
f
pins: high-impedance output, V
X
XT
During Reset Period
:
:
XT1 oscillation clock
X1 oscillation clock
CHAPTER 22 RESET FUNCTION
Block Diagram and 1.5
LC3
/P02 pin, CAPH/P00 pin,
Outline of
797