UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 326

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
6.7.5 Operation as input signal high-/low-level width measurement
level width/low-level width) of TIpq can be measured. The signal width of TIpq can be calculated by the following
expression.
set.
counter counts up in synchronization with the count clock. When the valid capture edge (falling edge of TIpq when the
high-level width is to be measured) is detected later, the count value is transferred to TDRpq and, at the same time,
INTTMpq is output. If the counter overflows at this time, the OVFpq bit of the TSRpq register is set to 1. If the counter
does not overflow, the OVFpq bit is cleared. TCRpq stops at the value “value transferred to TDRpq + 1”, and the TIpq pin
start edge detection wait status is set. After that, the above operation is repeated.
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
of the TSRpq register is set to 1. However, the OVFpq bit is configured as an integral flag, and the correct interval value
cannot be measured if an overflow occurs more than once.
and CISpq0 bits of the TMRpq register.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Remark
By starting counting at one edge of TIpq and capturing the number of counts at another edge, the signal width (high-
TCRpq operates as an up counter in the capture & one-count mode.
When the channel start trigger (TSpq) is set to 1, TEpq is set to 1 and the TIpq pin start edge detection wait status is
When the TIpq start valid edge (rising edge of TIpq when the high-level width is to be measured) is detected, the
As soon as the count value has been captured to the TDRpq register, the OVFpq bit of the TSRpq register is updated
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVFpq bit
Whether the high-level width or low-level width of the TIpq pin is to be measured can be selected by using the CISpq1
Because this function is used to measure the signal width of the TIpq pin input, TSpq cannot be set to 1 while TEpq is 1.
CISpq1, CISpq0 of TMRpq = 10B: Low-level width is measured.
CISpq1, CISpq0 of TMRpq = 11B: High-level width is measured.
Signal width of TIpq input = Period of count clock × ((10000H × TSRpq: OVF) + (Capture value of TDRpq + 1))
Caution The TIpq pin input is sampled using the operating clock selected with the CKSpq bit of the
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
TMRpq register, so an error equal to the number of operating clocks occurs.
CHAPTER 6 TIMER ARRAY UNIT
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