UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 414

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
(4) Timer trigger mode (Single conversion mode)
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
<1> Timer trigger mode is set and a timer trigger wait state is entered by setting bit 7 (ADTMD) of A/D converter mode
<2> When the timer trigger signal is detected, bit 7 (ADCS) of the A/D converter mode register (ADM) is automatically
<3> When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result
<4> Even if ADS is rewritten during an A/D conversion operation, the A/D conversion operation performed at that time
<5> If a timer trigger signal is generated during A/D conversion, the A/D conversion operation under execution is
<6> When 0 is written to ADTMD while A/D conversion operation is stopped (ADCS = 0), the software trigger mode is
Note Leave at least enough time for A/D conversion to finish between each generation of the timer trigger signal.
Remark 78K0R/LF3:
A/D conversion
Timer trigger
register 1 (ADM1) to 1.
set to 1 and A/D conversion of the voltage applied to the analog input pin specified using the analog input
channel specification register (ADS) starts.
register (ADCR, ADCRH), and an interrupt request signal (INTAD) is generated. When one A/D conversion has
been completed, ADCS is automatically cleared and a timer trigger wait state is entered.
is continued. The channel will be switched when the next A/D conversion operation starts.
stopped and restarted from the beginning. At this time, the conversion result immediately before is retained.
set and A/D conversion operation is not started, even if a timer trigger signal is generated.
ADTMD
ADCRH
INTAD
ADCR,
ADCS
78K0R/LG3, 78K0R/LH3:
<1> ADTMD = 1
Wait
state
<2> Timer trigger generation
Figure 10-19. Timer trigger mode (Single conversion mode)
ANIn
<3> A/D conversion
is completed
n = 0 to 6, 15, m = 0 to 6, 15
n = 0 to 10, 15, m = 0 to 10, 15
Note
Wait state
<2> Timer trigger generation
<4> Rewriting
ANIn
ADS
Conversion is
not stopped
ANIn
<3> A/D conversion
is completed
Wait state
<2> Timer trigger generation
Conversion operation
under execution is
stopped, and restarted
from the beginning
ANIn
CHAPTER 10 A/D CONVERTER
ANIm
<5> Timer trigger generation
ANIm
<3> A/D conversion
is completed
<6> ADTMD = 0
Wait
state
ANIm
414