UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 870

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Instruction
16-bit
data
transfer
8-bit
operation
Group
2.
3.
4.
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
Mnemonic
MOVW
XCHW
ONEW
CLRW
ADD
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
When the program memory area is accessed.
Except rp = AX
Except r = A
register (CKC).
AX, ES:[HL + byte]
ES:[HL + byte], AX
AX, ES:word[B]
ES:word[B], AX
AX, ES:word[C]
ES:word[C], AX
AX, ES:word[BC]
ES:word[BC], AX
BC, ES:!addr16
DE, ES:!addr16
HL, ES:!addr16
AX, rp
AX
BC
AX
BC
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, ES:!addr16
A, ES:[HL]
A, ES:[HL + byte]
A, ES:[HL + B]
A, ES:[HL + C]
Operands
Note 3
Note 4
Bytes
Table 30-5. Operation List (6/17)
3
3
4
4
4
4
4
4
4
4
4
1
1
1
1
1
2
3
2
2
2
3
1
2
2
2
4
2
3
3
3
Note 1 Note 2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
2
2
2
2
2
Clocks
5
−
5
−
5
−
5
−
5
5
5
−
−
−
−
−
−
−
−
−
−
4
4
4
4
4
5
5
5
5
5
AX ← ((ES, HL) + byte)
((ES, HL) + byte) ← AX
AX ← ((ES, B) + word)
((ES, B) + word) ← AX
AX ← ((ES, C) + word)
((ES, C) + word) ← AX
AX ← ((ES, BC) + word)
((ES, BC) + word) ← AX
BC ← (ES, addr16)
DE ← (ES, addr16)
HL ← (ES, addr16)
AX ←→ rp
AX ← 0001H
BC ← 0001H
AX ← 0000H
BC ← 0000H
A, CY ← A + byte
(saddr), CY ← (saddr) + byte
A, CY ← A + r
r, CY ← r + A
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, CY ← A + (HL + byte)
A, CY ← A + (HL + B)
A, CY ← A + (HL + C)
A, CY ← A + (ES, addr16)
A,CY ← A + (ES, HL)
A,CY ← A + ((ES, HL) + byte)
A,CY ← A + ((ES, HL) + B)
A,CY ← A + ((ES, HL) + C)
CPU
) selected by the system clock control
Operation
CHAPTER 30 INSTRUCTION SET
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Flag
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
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