UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 386

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0R/Lx3
8.4.3 Setting window open period of watchdog timer
(000C0H). The outline of the window is as follows.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte
• If “ACH” is written to WDTE during the window open period, the watchdog timer is cleared and starts counting again.
• Even if “ACH” is written to WDTE during the window close period, an abnormality is detected and an internal reset
Example: If the window open period is 50%
Caution When data is written to WDTE for the first time after reset release, the watchdog timer is cleared in
The window open period to be set is as follows.
Cautions 1. The watchdog timer continues its operation during self-programming of the flash memory and
signal is generated.
any timing regardless of the window open time, as long as the register is written before the overflow
time, and the watchdog timer starts counting again.
2. When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period is 100%
WINDOW1
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
regardless of the values of WINDOW1 and WINDOW0.
1
0
0
1
Counting
starts
Table 8-4. Setting Window Open Period of Watchdog Timer
Internal reset signal is generated
if "ACH" is written to WDTE.
WINDOW0
Window close period (50%)
0
1
0
1
Setting prohibited
50%
75%
100%
Window Open Period of Watchdog Timer
Counting starts again when
"ACH" is written to WDTE.
Window close period (50%)
CHAPTER 8 WATCHDOG TIMER
Overflow
time
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