UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 382

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
8.2 Configuration of Watchdog Timer
byte.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
WDCS2 to WDCS0 of
The watchdog timer includes the following hardware.
How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option
option byte (000C0H)
WINDOW0 of option
WDTON of option
WDTINT of option
WINDOW1 and
byte (000C0H)
byte (000C0H)
byte (000C0H)
f
IL
Remark For the option byte, see CHAPTER 26 OPTION BYTE.
Watchdog timer interval interrupt
Window open period
Controlling counter operation of watchdog timer
Overflow time of watchdog timer
Controlling counter operation of watchdog timer
(in HALT/STOP mode)
Control register
controller
Clock
input
Setting of Watchdog Timer
(Count value overflow time
Item
Watchdog timer enable
Window size check
Table 8-2. Setting of Option Bytes and Watchdog Timer
register (WDTE)
Interval time controller
counter
Figure 8-1. Block Diagram of Watchdog Timer
20-bit
Table 8-1. Configuration of Watchdog Timer
Count clear
signal
f
IL
Watchdog timer enable register (WDTE)
/2
7
to f
Internal bus
IL
/2
×
17
3/4)
decision signal
Selector
Window size
WDTE except ACH
Write detector to
Bit 7 (WDTINT)
Bits 6 and 5 (WINDOW1, WINDOW0)
Bit 4 (WDTON)
Bits 3 to 1 (WDCS2 to WDCS0)
Bit 0 (WDSTBYON)
Overflow signal
Configuration
Option Byte (000C0H)
CHAPTER 8 WATCHDOG TIMER
controller
output
Reset
Interval time interrupt
Internal reset signal
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