UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 247

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
78K0R/Lx3
5.6.5 CPU clock status transition diagram
Notes 1.
Remarks 1. If the low-power-supply detector (LVI) is set to ON by default by the option bytes, the reset will not be
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Oscillatable
DSC oscillation: Operating
Figure 5-15 shows the CPU clock status transition diagram of this product.
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Cannot be selected by CPU
XT1 oscillation:
Cannot be selected by CPU
DSC oscillation: Operating
2.
3.
2. DSC: 20 MHz internal high-speed oscillation clock
After reset release, an operation at one of the following operating frequencies is started, because f
has been selected by setting the system clock control register (CKC) to 09H.
• When 1 MHz has been selected by using the option byte: 500 kHz (1 MHz/2)
• When 8 MHz or 20 MHz has been selected by using the option byte: 4 MHz (8 MHz/2)
Specify 20 MHz internal oscillation after checking that V
20 MHz internal oscillation cannot be used if 1 MHz internal oscillation is selected by using the option byte.
released until the power supply voltage (V
After the reset operation, the status will shift to (B) in the above figure.
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Operating
DSC oscillation: Stops
(G)
DSC oscillation
→ HALT
(K)
CPU:
XT1 oscillation
Notes 2, 3
→ HALT
CPU:
Operating with
DSC oscillation
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation: Selectable by CPU
DSC oscillation: Selectable by CPU
CPU:
Figure 5-15. CPU Clock Status Transition Diagram
(D)
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation: Operating
DSC oscillation: Stops
(J)
Operating with
XT1 oscillation
CPU:
Internal high-speed
oscillation: Selectable by CPU
X1 oscillation/EXCLK input:
Operating
XT1 oscillation:
Selectable by CPU
DSC oscillation: Stops
(A)
DD
) exceeds 2.07 V±0.2 V.
(B)
(C)
with X1 oscillation or
with internal high-
Reset release
speed oscillation
CPU: Operating
CPU: Operating
Power ON
EXCLK input
(F)
oscillation/EXCLK
input → HALT
DD
CPU: X1
Note 1
is at least 2.7 V.
Internal high-speed
oscillation: Oscillatable
X1 oscillation/EXCLK input:
Operating
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation: Stops (input port mode)
DSC oscillation: Stops
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation: Stops (input port mode)
DSC oscillation: Stops
CHAPTER 5 CLOCK GENERATOR
(H)
CPU: Internal high-
CPU: Internal high-
oscillation/EXCLK
(E)
speed oscillation
speed oscillation
(I)
input → STOP
→ STOP
→ HALT
CPU: X1
V
V
V
DD
DD
DD
< 1.61 V±0.09
≥ 1.61 V±0.09
≥ 1.8 V
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input:
Stops
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Internal high-speed
oscillation: Stops
X1 oscillation/EXCLK
input: Stops
XT1 oscillation: Oscillatable
DSC oscillation: Stops
CLK
= f
IH
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