UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 244

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0R/Lx3
5.6.3 Example of controlling subsystem clock
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The following describes examples of setting procedures for the following cases.
(1) When oscillating subsystem clock
(2) When using subsystem clock as CPU clock
(3) When stopping subsystem clock
The subsystem clock can be oscillated by connecting a crystal resonator to the XT1 and XT2 pins.
When the subsystem clock is not used, the XT1/P123 and XT2/P124 pins can be used as input port pins.
Caution The XT1/P123 and XT2/P124 pins are in the input port mode after a reset release.
Caution When the subsystem clock is used as the CPU clock, the subsystem clock is also supplied to the
(1) Example of setting procedure when oscillating the subsystem clock
(b) To stop internal high-speed oscillation clock by setting HIOSTOP to 1
Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting HIOSTOP to 1. In addition, stop
<1> Setting P123/XT1 and P124/XT2 pins (CMC register)
<2> Controlling oscillation of subsystem clock (CSC register)
<1> Confirming the CPU clock status (CKC register)
<2> Stopping the internal high-speed oscillation clock (CSC register)
Remark For setting of the P121/X1 and P122/X2 pins, see 5.6.1 Example of controlling high-speed
If XTSTOP is cleared to 0, the XT1 oscillator starts oscillating.
peripheral hardware (except the real-time counter, timer array unit (when f
of TI0mn input, or the valid edge of INTRTCI is selected as the count clock), clock output/buzzer
output, and watchdog timer). At this time, the operations of the A/D converter and IICA are not
guaranteed.
describing the various peripheral hardware as well as CHAPTER 31 ELECTRICAL SPECIFICATIONS.
CLS
EXCLK
0
0
1
Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed
oscillation clock.
When CLS = 0 and MCS = 0, the internal high-speed oscillation clock is supplied to the CPU, so change
the CPU clock to the high-speed system clock or subsystem clock.
When HIOSTOP is set to 1, internal high-speed oscillation clock is stopped.
0/1
peripheral hardware that is operating on the internal high-speed oscillation clock.
system clock.
OSCSEL
MCS
0
1
×
For the operating characteristics of the peripheral hardware, refer to the chapters
0/1
Internal high-speed oscillation clock or 20 MHz internal high-speed
oscillation clock
High-speed system clock
Subsystem clock
0
0
OSCSELS
1
CPU Clock Status
0
0
AMPHS1
0/1
CHAPTER 5 CLOCK GENERATOR
AMPHS0
0/1
SUB
/2, f
AMPH
0/1
SUB
/4, the valid edge
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