UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 210

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
−
−
√
√
√
√
√
√
−
−
√
Notes 1. To use the P121 to P124 pins for main system clock resonator connection (X1, X2), subsystem clock
Remark ×:
−
−
√
√
√
√
√
√
√
√
√
√ P86
√ P87
√ P110, P111
√ P120
√ P121
√ P122
√ P123
√ P124
√ P150
√ P151, P152
√ P157
Table 4-11. Settings of Port Mode Register and Output Latch When Using Alternate Function (4/5)
2. The P150/ANI8/AMP2+, P151/ANI9, P152/ANI10, P157/ANI15/AV
−:
PFALL: Port function register
ISC:
PM××:
P××:
resonator connection (XT1, XT2), or main system clock external clock input (EXCLK), the X1 oscillation
mode, XT1 oscillation mode, or external clock input mode must be set, respectively, by using the clock
operation mode control register (CMC). CMC can be written only once after reset release (for details, refer
to 5.3 (1) Clock operation mode control register (CMC)). The reset value of CMC is 00H (both P121 to
P124 are input port pins).
on the settings of the A/D port configuration register (ADPC), port mode register 2 (PM2), analog input
channel specification register (ADS), operational amplifier control register (OAC), and analog reference
voltage control register (ADVRC). Refer to 4.2.16 Port 15.
Pin Name
Note 2
Note 2
Note 2
don’t care
Not applicable
Input switch control register
Port mode register
Port output latch
TI12
TO12
TI13
TO13
ANO0, ANO1
INTP0
EXLVI
X1
X2
EXCLK
XT1
XT2
ANI8
AMP2+
ANI9, ANI10
ANI15
AV
Note 1
Note 1
REFM
Note 1
Note 1
Function Name
Note 1
Note 1
Note 1
Alternate Function
Input
Output
Input
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
I/O
−
−
−
−
(PFxxx)
PFALL
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ISC0 = 0
REFM
(ISCx)
CHAPTER 4 PORT FUNCTIONS
ISC
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
pins are as shown below depending
PM××
×
×
×
×
×
1
0
1
0
0
1
1
1
1
1
1
1
P××
×
0
×
0
×
×
×
×
×
×
×
×
×
×
×
×
×
210