UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 919

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
78K0R/Lx3
(2) Serial interface: Serial array unit (14/18)
Notes 1.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
SCKp cycle time
SCKp high-/low-level
width
SIp setup time
(to SCKp↑)
SIp hold time
(from SCKp↑)
Delay time from SCKp↓ to
SOp output
(Caution and Remark are given on the next page.)
(T
(g) Communication at different potential (2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
A
2.
3.
Parameter
= −40 to +85°C, 2.7 V ≤ V
Note 1
Note 3
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2
CSI mode connection diagram (communication at different potential)
t
t
t
t
t
t
KCY2
KH2
KL2
SIK2
KSI2
KSO2
Symbol
,
<Slave>
DD
microcontrollers
78K0R/Lx3
= EV
4.0 V ≤ V
2.7 V ≤ V
2.7 V ≤ V
2.3 V ≤ V
4.0 V ≤ V
2.7 V ≤ V
4.0 V ≤ V
C
2.7 V ≤ V
C
b
b
= 30 pF, R
= 30 pF, R
DD
DD
b
DD
b
DD
DD
DD
DD
≤ 5.5 V, V
≤ 4.0 V
≤ 2.7 V
≤ 5.5 V,
< 4.0 V,
≤ 5.5 V, 2.7 V ≤ V
< 4.0 V, 2.3 V ≤ V
≤ 5.5 V, 2.7 V ≤ V
< 4.0 V, 2.3 V ≤ V
SCKp
b
b
SOp
= 1.4 kΩ
= 2.7 kΩ
SIp
Conditions
SS
13.6 MHz < f
6.8 MHz < f
f
18.5 MHz < f
14.8 MHz < f
11.1 MHz < f
7.4 MHz < f
3.7 MHz < f
f
MCK
MCK
V
= EV
b
≤ 6.8 MHz
≤ 3.7 MHz
R
b
b
b
b
b
≤ 4.0 V
≤ 4.0 V,
≤ 2.7 V
≤ 2.7 V,
SS
MCK
MCK
MCK
= AVss = 0 V)
MCK
MCK
MCK
MCK
CHAPTER 31 ELECTRICAL SPECIFICATIONS
≤ 13.6 MHz
≤ 11.1 MHz
≤ 7.4 MHz
≤ 18.5 MHz
≤ 14.8 MHz
SCK
SO
SI
User's device
1/f
f
f
10/f
16/f
14/f
12/f
10/f
KCY2
KCY2
8/f
6/f
8/f
6/f
MIN.
MCK
20
35
90
MCK
MCK
MCK
MCK
MCK
MCK
MCK
MCK
MCK
/2 −
/2 −
+ 50
TYP.
2/f
2/f
MCK
MCK
MAX.
+ 230
+ 120
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
919