UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 718

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
17.3 Register Controlling Multiplier/Divider
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The multiplier/divider is controlled by using the multiplication/division control register (MDUC).
(1) Multiplication/division control register (MDUC)
MDUC is an 8-bit register that controls the operation of the multiplier/divider.
MDUC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: F00E8H
Note DIVST can only be set (1) in the division mode. In the division mode, division operation is started by setting
Cautions 1. Do not rewrite DIVMODE during operation processing (while DIVST is 1). If it is rewritten, the
Symbol
MDUC
(1) DIVST. DIVST is automatically cleared (0) when the operation ends. In the multiplication mode,
operation is automatically started by setting the multiplier and multiplicand to MDAH and MDAL, respectively.
2. DIVST cannot be cleared (0) by using software during division operation processing (while
DIVMODE
DIVMODE
DIVST
operation result will be an undefined value.
DIVST is 1).
<7>
Figure 17-5. Format of Multiplication/Division Control Register (MDUC)
0
1
0
1
Note
After reset: 00H
Multiplication mode
Division mode
Division operation processing complete
Starts division operation/division operation processing in progress
6
0
R/W
5
0
Operation mode (multiplication/division) selection
4
0
Division operation start/stop
3
0
CHAPTER 17 MULTIPLIER/DIVIDER
2
0
1
0
DIVST
<0>
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