UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 593

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Caution When bit 3 (TRC) of the IICA status register (IICS) is set to 1, WREL is set to 1 during the
Cautions concerning set timing
• For master reception:
• For master transmission: A stop condition cannot be generated normally during the acknowledge period.
• Cannot be set to 1 at the same time as STT.
• SPT can be set to 1 only when in master mode.
• When WTIM has been cleared to 0, if SPT is set to 1 during the wait period that follows output of eight clocks, note
• Setting SPT to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (SPT = 0)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared by LREL = 1 (exit from communications)
• When IICE = 0 (operation stop)
• Reset
Remark
that a stop condition will be generated during the high-level period of the ninth clock. WTIM should be changed from
0 to 1 during the wait period following the output of eight clocks, and SPT should be set to 1 during the wait period
that follows the output of the ninth clock.
SPT
0
1
ninth clock and wait is canceled, after which TRC is cleared and the SDA0 line is set to high
impedance. Release the wait performed while the TRC bit is 1 (transmission status) by
writing to the IICA shift register.
Bit 0 (SPT) becomes 0 when it is read after data setting.
Stop condition is not generated.
Stop condition is generated (termination of master device’s transfer).
Figure 15-6. Format of IICA Control Register 0 (IICCTL0) (4/4)
Cannot be set to 1 during transfer.
Can be set to 1 only in the waiting period when ACKE has been cleared to 0 and slave
has been notified of final reception.
Therefore, set it during the wait period that follows output of the ninth clock.
Stop condition trigger
Condition for setting (SPT = 1)
• Set by instruction
CHAPTER 15 SERIAL INTERFACE IICA
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