UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 659
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The following describes the operations in Figure 15-32 (4) Data ~ restart condition ~ address. After the operations
in steps <7> and <8>, the operations in steps <1> to <3> are performed. These steps return the processing to step
<3>, the data transmission step.
<7> When data transfer is complete, the slave device sends an ACK by hardware to the master device. The
<8> The master device and slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and
<i>
<ii>
<iii> The master device writes the address + R/W (transmission) to the IICA shift register (IICA) and transmits
ACK is detected by the master device (ACKD = 1) at the rising edge of the 9th clock.
both the master device and slave device issue an interrupt (INTIICA: end of transfer).
The slave device reads the received data and releases the wait status (WREL = 1).
The start condition trigger is set again by the master device (STT = 1) and a start condition (SDA0 = 0 and
SCL0 = 1) is generated once the bus clock line goes high (SCL0 = 1) and the bus data line goes low (SDA0
= 0) after the restart condition setup time has elapsed. When the start condition is subsequently detected,
the master device is ready to communicate once the bus clock line goes low (SCL0 = 0) after the hold time
has elapsed.
the slave address.
CHAPTER 15 SERIAL INTERFACE IICA
659
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