UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 970

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Subsystem
clock
control
CPU clock
status
transition
Timer
array unit
Function
XT1/P123,
XT2/P124
Subsystem clock
TCRmn:
Timer/counter
register mn
TDRmn: Timer
data register mn
PER0:
Peripheral
enable register 0
TPSm: Timer
clock select
register m
Details of
Function
−
−
The XT1/P123 and XT2/P124 pins are in the input port mode after a reset release.
When the subsystem clock is used as the CPU clock, the subsystem clock is also
supplied to the peripheral hardware (except the real-time counter, timer array unit
(when f
selected as the count clock), clock output/buzzer output, and watchdog timer). At
this time, the operations of the A/D converter and IICA are not guaranteed. For the
operating characteristics of the peripheral hardware, refer to the chapters describing
the various peripheral hardware as well as CHAPTER 31 ELECTRICAL
SPECIFICATIONS.
The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction.
Therefore, it is necessary to also set the value of the EXCLK and OSCSEL bits at the
same time.
procedure when oscillating the X1 clock or 5.6.1 (2) Example of setting procedure
when using the external main system clock.
Be sure to confirm that CLS = 0 when setting XTSTOP to 1. In addition, stop the
peripheral hardware if it is operating on the subsystem clock.
The subsystem clock oscillation cannot be stopped using the STOP instruction.
Set the clock after the supply voltage has reached the operable voltage of the clock
to be set (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Channel 5 of timer array unit 0 of the 78K0R/LF3 can be used only as an interval
timer.
Channel 6 of timer array unit 0 of the 78K0R/LF3 can be used only as an interval
timer, for PWM output (master channel), and for one-shot pulse output (master
channel when software trigger start is selected).
Channels 0 to 3 of timer array unit 1 of the 78K0R/LF3 and 78K0R/LG3 can be used
only as interval timers.
Channels 1, 5 to 7 of timer array unit 0 and channels 0 to 3 of timer array unit 1
cannot be used as frequency dividers.
The count value is not captured to TDRmn even when TCRmn is read.
TDRmn does not perform a capture operation even if a capture trigger is input, when
it is set to the compare function.
When setting the timer array unit, be sure to set TAUmEN to 1 first. If TAUmEN = 0,
writing to a control register of the timer array unit is ignored, and all read values are
default values.
Be sure to clear bits 15 to 8 to “0”.
SUB
/2, f
SUB
For EXCLK and OSCSEL bits, see 5.6.1 (1) Example of setting
/4, the valid edge of TI0mn input, or the valid edge of INTRTCI is
Cautions
APPENDIX C LIST OF CAUTIONS
249, 252
p.245
p.244
pp.244,
245
p.245
p.245
pp.248,
p.258
p.258
p.258
p.258
p.265
p.267
p.269
p.270
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