UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 657

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The meanings of <7> to <15> in (3) Data ~ data ~ stop condition in Figure 15-32 are explained below.
Remark <1> to <15> in Figure 15-32 represent the entire procedure for communicating data using the I
<7> When data transfer is complete, the slave device sends an ACK by hardware to the master device. The
<8> The master device and slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and
<9> The master device writes the data to transmit to the IICA shift register (IICA) and releases the wait status
<10> The slave device reads the received data and releases the wait status (WREL = 1). The master device then
<11> When data transfer is complete, the slave device sends an ACK by hardware to the master device. The
<12> The master device and slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and
<13> The slave device reads the received data and releases the wait status (WREL = 1).
<14> After a stop condition trigger is set, the bus data line is cleared (SDA0 = 0) and the bus clock line is set
<15> When a stop condition is generated, the slave device detects the stop condition and issues an interrupt
ACK is detected by the master device (ACKD = 1) at the rising edge of the 9th clock.
both the master device and slave device issue an interrupt (INTIICA: end of transfer).
that it set by the master device.
starts transferring data to the slave device.
ACK is detected by the master device (ACKD = 1) at the rising edge of the 9th clock.
both the master device and slave device issue an interrupt (INTIICA: end of transfer).
(SCL0 = 1). The stop condition is then generated by setting the bus data line (SDA0 = 1) after the stop
condition setup time has elapsed.
(INTIICA: stop condition).
Figure 15-32 (1) Start condition ~ address ~ data shows the processing from <1> to <6>, Figure 15-32
(2) Address ~ data ~ data shows the processing from <3> to <10>, and Figure 15-32 (3) Data ~ data ~
stop condition shows the processing from <7> to <15>.
CHAPTER 15 SERIAL INTERFACE IICA
2
C bus.
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