UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 452

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: F00F0H
(1) Peripheral enable register 0 (PER0)
(2) Serial clock select register m (SPSm)
Symbol
PER0
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that
is not used is stopped in order to reduce the power consumption and noise.
When serial array unit 0 is used, be sure to set bit 2 (SAU0EN) of this register to 1.
When serial array unit 1 is used, be sure to set bit 3 (SAU1EN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Note 78K0R/LG3, 78K0R/LH3 only
Cautions 1. When setting serial array unit m, be sure to set SAUmEN to 1 first. If SAUmEN = 0, writing to a
Remark m: Unit number (m = 0, 1)
SPSm is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly
supplied to each channel. CKm1 is selected by bits 7 to 4 of SPSm, and CKm0 is selected by bits 3 to 0.
Rewriting SPSm is prohibited when the register is in operation (when SEmn = 1).
SPSm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SPSm can be set with an 8-bit memory manipulation instruction with SPSmL.
Reset signal generation clears this register to 0000H.
SAUmEN
RTCEN
2. After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
<7>
0
1
After reset: 00H
control register of serial array unit m is ignored, and, even if the register is read, only the
default value is read (except for input switch control register (ISC), noise filter enable register
(NFEN0), port input mode registers (PIM1, PIM7), port output mode registers (POM1, POM7,
POM8), port mode registers (PM1, PM5, PM7, PM8), and port registers (P1, P5, P7, P8)).
elapsed.
Stops supply of input clock.
• SFR used by serial array unit m cannot be written.
• Serial array unit m is in the reset status.
Supplies input clock.
• SFR used by serial array unit m can be read/written.
DACEN
Figure 14-4. Format of Peripheral Enable Register 0 (PER0)
<6>
R/W
ADCEN
<5>
IICAEN
Control of serial array unit m input clock
<4>
Note
SAU1EN
<3>
CHAPTER 14 SERIAL ARRAY UNIT
SAU0EN
<2>
TAU1EN
<1>
TAU0EN
<0>
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