UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 102

• Manufacturer Part Number: UPD78F9502MA-CAC-A
• Description: 8BIT MCU, 4K FLASH, 128B RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F9502MA-CAC-A

• Controller Family/series: UPD78F
• No. Of I/o's: 8
• Ram Memory Size: 128Byte
• Cpu Speed: 10MHz
• No. Of Timers: 2
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

(4) Program status word (PSW)
8.4
8.4.1
corresponding interrupt mask flag is cleared to 0. If the interrupt enabled status is in effect (when the IE flag is set to
1), then the request is acknowledged as a vector interrupt.
shown in Table 8-3.
from the interrupt request assigned the highest priority.
102
Symbol
A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the
The time required to start the vectored interrupt servicing after a maskable interrupt request has been generated is
See Figures 8-7 and 8-8 for the interrupt request acknowledgment timing.
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
A pending interrupt is acknowledged when a status in which it can be acknowledged is set.
PSW
Interrupt Servicing Operation
Maskable interrupt request acknowledgment operation
The program status word is used to hold the instruction execution result and the current status of the interrupt
requests. The IE flag, used to enable and disable maskable interrupts, is mapped to PSW.
PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and
dedicated instructions (EI and DI). When a vectored interrupt is acknowledged, the PSW is automatically
saved to a stack, and the IE flag is reset to 0.
Reset signal generation sets PSW to 02H.
Cautions 2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag
IE
IE
7
0
1
Disabled
Enabled
Table 8-3. Time from Generation of Maskable Interrupt Request to Servicing
Z
6
(
request flag (
interrupts.
5
0
MK = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt
Figure 8-5. Program Status Word (PSW) Configuration
Note The wait time is maximum when an interrupt
Remark
9 clocks
AC
4
request is generated immediately before BT and
BF instructions.
Minimum Time
3
0
CHAPTER 8 INTERRUPT FUNCTIONS
IF = 0), then clear the interrupt mask flag (
1 clock:
Preliminary User’s Manual U18681EJ1V0UD
Whether to enable/disable interrupt acknowledgment
2
0
f
CPU
1
1
1
(f
CPU
CY
0
: CPU clock)
19 clocks
Maximum Time
After reset
Used in the execution of ordinary instructions
02H
Note
MK = 0), which will enable