UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 147

• Manufacturer Part Number: UPD78F9502MA-CAC-A
• Description: 8BIT MCU, 4K FLASH, 128B RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F9502MA-CAC-A

• Controller Family/series: UPD78F
• No. Of I/o's: 8
• Ram Memory Size: 128Byte
• Cpu Speed: 10MHz
• No. Of Timers: 2
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

14.8.2 Cautions on self programming function
14.8.3 Registers used for self-programming function
The following registers are used for the self-programming function.
The PD78F9500, 78F9501, 78F9502 have an area called a protect byte at address 0081H of the flash memory.
(1) Flash programming mode control register (FLPMC)
Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address pointer H compare register
No instructions can be executed while a self programming command is being executed. Therefore, clear and
restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self
programming. Refer to Table 14-8 for the time taken for the execution of self programming.
Interrupts that occur during self programming can be acknowledged after self programming mode ends. To avoid
this operation, disable interrupt servicing (by setting MK0 to FFH, and executing the DI instruction) before a
mode is shifted from the normal mode to the self programming mode with a specific sequence.
RAM is not used while a self programming command is being executed.
If the supply voltage drops or the reset signal is input while the flash memory is being written or erased,
writing/erasing is not guaranteed.
The value of the blank data set during block erasure is FFH.
Set the CPU clock so that it is 1 MHz or more during self programming.
Execute the NOP and HALT instructions immediately after executing a specific sequence to set self-programming
mode, then execute self programming. At this time, the HALT instruction is automatically released after 10 s
(MAX.) + 2 CPU clocks (f
If the clock of the oscillator or an external clock is selected as the system clock, execute the NOP and HALT
instructions immediately after executing a specific sequence to set self-programming mode, wait for 8 s after
releasing the HALT status, and then execute self programming.
Check FPRERR using a 1-bit memory manipulation instruction.
The state of the pins in self programming mode is the same as that in HALT mode.
Since the security function set via on-board/off-board programming is disabled in self programming mode, the
self programming command can be executed regardless of the security function setting. To disable write or erase
processing during self programming, set the protect byte.
(FLAPHC) to 0 before executing the self programming command. If the value of these bits is 1 when executing
the self programming command, there is a possibility that device does not operate normally.
Clear the value of the FLCMD register to 00H immediately before setting self-programming mode and normal
operation mode.
Flash programming mode control register (FLPMC)
Flash protect command register (PFCMD)
Flash status register (PFS)
Flash programming command register (FLCMD)
Flash address pointers H and L (FLAPH and FLAPL)
Flash address pointer H compare register and flash address pointer L compare register (FLAPHC and FLAPLC)
Flash write buffer register (FLW)
This register is used to set the operation mode when data is written to the flash memory in the self-
Data can be written to FLPMC only in a specific sequence (refer to 14.8.3 (2) Flash protect command
programming mode, and to read the set value of the protect byte.
register (PFCMD)) so that the application system does not stop by accident because of malfunction due to
noise or program hang-up.
CPU
).
Preliminary User’s Manual U18681EJ1V0UD
CHAPTER 14 FLASH MEMORY
147