UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 92

• Manufacturer Part Number: UPD78F9502MA-CAC-A
• Description: 8BIT MCU, 4K FLASH, 128B RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F9502MA-CAC-A

• Controller Family/series: UPD78F
• No. Of I/o's: 8
• Ram Memory Size: 128Byte
• Cpu Speed: 10MHz
• No. Of Timers: 2
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

7.4
7.4.1
the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.
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The operation clock of watchdog timer is fixed to low-speed internal oscillation clock.
After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
The following shows the watchdog timer operation after reset release.
1.
2.
3.
Notes 1.
Caution In this mode, operation of the watchdog timer cannot be stopped even during STOP instruction
A status transition diagram is shown below
Operation of Watchdog Timer
The status after reset release is as follows.
The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instruction
After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Watchdog timer operation when “low-speed internal oscillator cannot be stopped” is selected by
option byte
Operation clock: Low-speed internal oscillation clock
Cycle: 2
Counting starts
Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
2.
execution. For 8-bit timer H1 (TMH1), a division of the low-speed internal oscillation clock can be
selected as the count source, so clear the watchdog timer using the interrupt request of TMH1
before the watchdog timer overflows after STOP instruction execution. If this processing is not
performed, an internal reset signal is generated when the watchdog timer overflows after STOP
instruction execution.
The operation clock (low-speed internal oscillation clock) cannot be changed. If any value is written to
bits 3 and 4 (WDCS3, WDCS4) of WDTM, it is ignored.
As soon as WDTM is written, the counter of the watchdog timer is cleared.
Notes 1, 2
18
/f
RL
.
(546.13 ms: At operation with f
Preliminary User’s Manual U18681EJ1V0UD
CHAPTER 7 WATCHDOG TIMER
RL
= 480 kHz (MAX.))