UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 223

• Manufacturer Part Number: UPD78F9502MA-CAC-A
• Description: 8BIT MCU, 4K FLASH, 128B RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F9502MA-CAC-A

• Controller Family/series: UPD78F
• No. Of I/o's: 8
• Ram Memory Size: 128Byte
• Cpu Speed: 10MHz
• No. Of Timers: 2
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

8-bit timer
H1
Watchdog
timer
Function
CMP11: 8-bit
timer H
compare
register 11
TMHMD1: 8-bit
timer H mode
register 1
PWM output
WDTM:
Watchdog timer
mode register
WDTE:
Watchdog timer
enable register
When “low-
speed internal
oscillator cannot
be stopped” is
selected by
option byte
when “low-
speed internal
oscillator can be
stopped by
software” is
selected by
option byte
Details of
Function
In the PWM output mode, be sure to set CMP11 when starting the timer count
operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0)
(be sure to set again even if setting the same value to CMP11).
When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited.
In the PWM output mode, be sure to set 8-bit timer H compare register 11
(CMP11) when starting the timer count operation (TMHE1 = 1) after the timer
count operation was stopped (TMHE1 = 0) (be sure to set again even if setting
the same value to the CMP11 register).
In PWM output mode, the setting value for the CMP11 register can be changed
during timer count operation. However, three operation clocks (signal selected
using the CKS12 to CKS10 bits of the TMHMD1 register) or more are required to
transfer the register value after rewriting the CMP11 register value.
Be sure to set the CMP11 register when starting the timer count operation
(TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure
to set again even if setting the same value to the CMP11 register).
Make sure that the CMP11 register setting value (M) and CMP01 register setting
value (N) are within the following range.
Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values.
After reset is released, WDTM can be written only once by an 8-bit memory
manipulation instruction. If writing is attempted a second time, an internal reset
signal is generated. However, at the first write, if “1” and “x” are set for WDCS4
and WDCS3 respectively and the watchdog timer is stopped, then the internal
reset signal does not occur even if the following are executed.
WDTM cannot be set by a 1-bit memory manipulation instruction.
When using the flash memory self programming by self writing, set the overflow
time for the watchdog timer so that enough everflow time is secured (Example 1-
byte writing: 200 s MIN., 1-block deletion: 10 ms MIN.).
If a value other than ACH is written to WDTE, an internal reset signal is
generated.
If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
signal is generated.
The value read from WDTE is 9AH (this differs from the written value (ACH)).
In this mode, operation of the watchdog timer cannot be stopped even during
STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the low-
speed internal oscillation clock can be selected as the count source, so clear the
watchdog timer using the interrupt request of TMH1 before the watchdog timer
overflows after STOP instruction execution. If this processing is not performed,
an internal reset signal is generated when the watchdog timer overflows after
STOP instruction execution.
In this mode, watchdog timer operation is stopped during HALT/STOP instruction
execution. After HALT/STOP mode is released, counting is started again using
the operation clock of the watchdog timer set before HALT/STOP instruction
execution by WDTM. At this time, the counter is not cleared to 0 but holds its
value.
00H
Second write to WDTM
1-bit memory manipulation instruction to WDTE
Writing of a value other than “ACH” to WDTE
CMP11 (M) < CMP01 (N)
Preliminary User’s Manual U18681EJ1V0UD
APPENDIX C LIST OF CAUTIONS
FFH
Cautions
p. 74
p. 76
p. 76
p. 82
p. 82
p. 82
p. 90
p. 91
p. 91
p. 91
p. 91
p. 91
p. 91
p. 92
p. 94
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