UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 169

• Manufacturer Part Number: UPD78F9502MA-CAC-A
• Description: 8BIT MCU, 4K FLASH, 128B RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F9502MA-CAC-A

• Controller Family/series: UPD78F
• No. Of I/o's: 8
• Ram Memory Size: 128Byte
• Cpu Speed: 10MHz
• No. Of Timers: 2
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

14.8.9 Example of internal verify operation in self programming mode
An example of the internal verify operation in self programming mode is explained below.
<1> Set 01H (internal verify 1) to the flash program command register (FLCMD).
<2> Set the number of block for which internal verify is performed, to flash address pointer H (FLAPH).
<3> Sets the flash address pointer L (FLAPL) to 00H.
<4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Sets the flash address pointer L compare register (FLAPLC) to FFH.
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
<10> Internal verify processing is abnormally terminated.
<11> Internal verify processing is normally terminated.
<1> Set 02H (internal verify 2) to the flash program command register (FLCMD).
<2> Set the number of block for which internal verify is performed, to flash address pointer H (FLAPH).
<3> Sets flash address pointer L (FLAPL) to the start address.
<4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Sets flash address pointer L compare register (FLAPLC) to the end address.
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
<10> Internal verify processing is abnormally terminated.
<11> Internal verify processing is normally terminated.
Note This setting is not required when the watchdog timer is not used.
Internal verify 1
Internal verify 2
HALT instruction if self programming has been executed.)
Abnormal
Normal
HALT instruction if self programming has been executed.)
Abnormal
Normal
<10>
<11>
<10>
<11>
Preliminary User’s Manual U18681EJ1V0UD
CHAPTER 14 FLASH MEMORY
Note
Note
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