UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 70

• Manufacturer Part Number: UPD78F9502MA-CAC-A
• Description: 8BIT MCU, 4K FLASH, 128B RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F9502MA-CAC-A

• Controller Family/series: UPD78F
• No. Of I/o's: 8
• Ram Memory Size: 128Byte
• Cpu Speed: 10MHz
• No. Of Timers: 2
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

5.6
(1) Clock to peripheral hardware
(2) Low-speed internal oscillation clock
70
The following two types of clocks are supplied to the peripheral hardware.
The clock to the peripheral hardware is supplied by dividing the system clock (f
by the pre-processor clock control register (PPCC).
Three types of frequencies are selectable: “f
peripheral hardware.
The low-speed internal oscillator of the clock oscillator for interval time generation is always started after release
of reset, and oscillates at 240 kHz (TYP.).
It can be specified by the option byte whether the low-speed internal oscillator can or cannot be stopped by
software. If it is specified that the low-speed internal oscillator can be stopped by software, oscillation can be
started or stopped by using the low-speed internal oscillation mode register (LSRCM). If it is specified that it
cannot be stopped by software, the clock source of WDT is fixed to the low-speed internal oscillation clock (f
The low-speed internal oscillator is independent of the CPU clock. If it is used as the source clock of WDT,
therefore, a hang-up can be detected even if the CPU clock is stopped. If the low-speed internal oscillator is used
as a count clock source of 8-bit timer H1, 8-bit timer H1 can operate even in the standby status.
Table 5-4 shows the operation status of the low-speed internal oscillator when it is selected as the source clock of
WDT and the count clock of 8-bit timer H1. Figure 5-10 shows the status transition of the low-speed internal
oscillator.
Clock to peripheral hardware (f
Low-speed internal oscillation clock (f
Operation of Clock Generator Supplying Clock to Peripheral Hardware
Can be stopped by
software
Cannot be stopped
Option Byte Setting
PPCC1
0
0
1
1
Table 5-4. Operation Status of Low-Speed Internal Oscillator
LSRSTOP = 1
LSRSTOP = 0
LSRSTOP = 1
LSRSTOP = 0
PPCC0
0
1
0
1
XP
Table 5-3. Clocks to Peripheral Hardware
)
CHAPTER 5 CLOCK GENERATORS
Preliminary User’s Manual U18681EJ1V0UD
f
f
f
Setting prohibited
RL
X
X
X
/2
/2
)
2
Operation mode
Standby
Operation mode
Standby
X
CPU Status
”, “f
Selection of clock to peripheral hardware (f
X
/2”, and “f
X
/2
Stopped
Operates
Stopped
Stopped
Operates
2
”. Table 5-3 lists the clocks supplied to the
WDT Status
X
). The division ratio is selected
Stopped
Operates
Stopped
Operates
TMH1 Status
XP
)
RL
).