UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 126

• Manufacturer Part Number: UPD78F9502MA-CAC-A
• Description: 8BIT MCU, 4K FLASH, 128B RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F9502MA-CAC-A

• Controller Family/series: UPD78F
• No. Of I/o's: 8
• Ram Memory Size: 128Byte
• Cpu Speed: 10MHz
• No. Of Timers: 2
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

12.4 Operation of Low-Voltage Detector
126
The low-voltage detector can be used in the following two modes.
The operation is set as follows.
(1) When used as reset
Used as reset
Compares the supply voltage (V
V
Used as interrupt
Compares the supply voltage (V
when V
DD
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select
<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<4> Use software to instigate a wait of at least 0.2 ms.
<5> Wait until “supply voltage (V
<6> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (V
Figure 12-4 shows the timing of generating the internal reset signal of the low-voltage detector. Numbers <1>
to <6> in this figure correspond to <1> to <6> above.
Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately
< V
When starting operation
When stopping operation
Either of the following procedures must be executed.
When using 8-bit memory manipulation instruction: Write 00H to LVIM.
When using 1-bit memory manipulation instruction: Clear LVIMD to 0 and LVION to 0 in that order.
DD
register (LVIS).
voltage (V
LVI
, and releases internal reset when V
< V
2. If supply voltage (V
LVI
after the processing in <3>.
signal is not generated.
.
LVI
)).
CHAPTER 12 LOW-VOLTAGE DETECTOR
DD
DD
) and detection voltage (V
Preliminary User’s Manual U18681EJ1V0UD
DD
) and detection voltage (V
DD
) ≥ detection voltage (V
) ≥ detection voltage (V
DD
≥ V
LVI
.
LVI
LVI
LVI
)” at bit 0 (LVIF) of LVIM is confirmed.
LVI
), and generates an internal reset signal when
), and generates an interrupt signal (INTLVI)
) when LVIMD is set to 1, an internal reset
DD
) < detection